riscv/processor.cc

   1 #include "processor.h"
   2 #include <bfd.h>
   3 #include <dis-asm.h>
   4 #include <cmath>
   5 #include <cstdlib>
   6 #include <iostream>
   7 #include "common.h"
   8 #include "config.h"
   9 #include "sim.h"
  10 #include "softfloat.h"
  11
  12 processor_t::processor_t(sim_t* _sim, char* _mem, size_t _memsz)
  13   : sim(_sim), mmu(_mem,_memsz)
  14 {
  15   memset(R,0,sizeof(R));
  16   memset(FR,0,sizeof(FR));
  17   pc = 0;
  18   evec = 0;
  19   epc = 0;
  20   badvaddr = 0;
  21   cause = 0;
  22   tid = 0;
  23   pcr_k0 = 0;
  24   pcr_k1 = 0;
  25   tohost = 0;
  26   fromhost = 0;
  27   count = 0;
  28   compare = 0;
  29   interrupts_pending = 0;
  30   set_sr(SR_S | (support_64bit ? SR_SX : 0));
  31   set_fsr(0);
  32
  33   memset(counters,0,sizeof(counters));
  34
  35   // a few assumptions about endianness, including freg_t union
  36   static_assert(BYTE_ORDER == LITTLE_ENDIAN);
  37   static_assert(sizeof(freg_t) == 8);
  38   static_assert(sizeof(reg_t) == 8);
  39
  40   static_assert(sizeof(insn_t) == 4);
  41   static_assert(sizeof(uint128_t) == 16 && sizeof(int128_t) == 16);
  42 }
  43
  44 void processor_t::init(uint32_t _id)
  45 {
  46   id = _id;
  47 }
  48
  49 void processor_t::set_sr(uint32_t val)
  50 {
  51   sr = val & ~SR_ZERO;
  52   if(!support_64bit)
  53     sr &= ~(SR_SX | SR_UX);
  54   if(!support_fp)
  55     sr &= ~SR_EF;
  56
  57   gprlen = ((sr & SR_S) ? (sr & SR_SX) : (sr & SR_UX)) ? 64 : 32;
  58 }
  59
  60 void processor_t::set_fsr(uint32_t val)
  61 {
  62   fsr = val & ~FSR_ZERO;
  63   softfloat_roundingMode = (fsr & FSR_RD) >> FSR_RD_SHIFT;
  64 }
  65
  66 void processor_t::step(size_t n, bool noisy)
  67 {
  68   size_t i = 0;
  69   while(1) try
  70   {
  71     for( ; i < n; i++)
  72     {
  73       uint32_t interrupts = interrupts_pending & ((sr & SR_IM) >> SR_IM_SHIFT);
  74       if((sr & SR_ET) && interrupts)
  75       {
  76         for(int i = 0; interrupts; i++, interrupts >>= 1)
  77           if(interrupts & 1)
  78             throw trap_t(16+i);
  79       }
  80
  81       insn_t insn = mmu.load_insn(pc);
  82
  83       reg_t npc = pc+sizeof(insn);
  84
  85       if(noisy)
  86         disasm(insn,pc);
  87
  88       #include "execute.h"
  89
  90       pc = npc;
  91       R[0] = 0;
  92
  93       if(count++ == compare)
  94         interrupts_pending |= 1 << TIMER_IRQ;
  95     }
  96     return;
  97   }
  98   catch(trap_t t)
  99   {
 100     i++;
 101     take_trap(t,noisy);
 102   }
 103 }
 104
 105 void processor_t::take_trap(trap_t t, bool noisy)
 106 {
 107   demand(t < NUM_TRAPS, "internal error: bad trap number %d", int(t));
 108   demand(sr & SR_ET, "error mode on core %d!\ntrap %s, pc 0x%016llx",
 109          id, trap_name(t), (unsigned long long)pc);
 110   if(noisy)
 111     printf("core %3d: trap %s, pc 0x%016llx\n",
 112            id, trap_name(t), (unsigned long long)pc);
 113
 114   set_sr((((sr & ~SR_ET) | SR_S) & ~SR_PS) | ((sr & SR_S) ? SR_PS : 0));
 115   cause = t;
 116   epc = pc;
 117   pc = evec;
 118   badvaddr = mmu.get_badvaddr();
 119 }
 120
 121 void processor_t::disasm(insn_t insn, reg_t pc)
 122 {
 123   printf("core %3d: 0x%016llx (0x%08x) ",id,(unsigned long long)pc,insn.bits);
 124
 125   #ifdef RISCV_HAVE_LIBOPCODES
 126   disassemble_info info;
 127   INIT_DISASSEMBLE_INFO(info, stdout, fprintf);
 128   info.flavour = bfd_target_unknown_flavour;
 129   info.arch = bfd_arch_mips;
 130   info.mach = 101; // XXX bfd_mach_mips_riscv requires modified bfd.h
 131   info.endian = BFD_ENDIAN_LITTLE;
 132   info.buffer = (bfd_byte*)&insn;
 133   info.buffer_length = sizeof(insn);
 134   info.buffer_vma = pc;
 135
 136   demand(print_insn_little_mips(pc, &info) == sizeof(insn), "disasm bug!");
 137   #else
 138   printf("unknown");
 139   #endif
 140   printf("\n");
 141 }