riscv/processor.cc

   1 // See LICENSE for license details.
   2
   3 #include "processor.h"
   4 #include "common.h"
   5 #include "config.h"
   6 #include "sim.h"
   7 #include "disasm.h"
   8 #include <cinttypes>
   9 #include <cmath>
  10 #include <cstdlib>
  11 #include <iostream>
  12 #include <assert.h>
  13 #include <limits.h>
  14
  15 processor_t::processor_t(sim_t* _sim, mmu_t* _mmu, uint32_t _id)
  16   : sim(*_sim), mmu(*_mmu), id(_id), opcode_bits(0)
  17 {
  18   reset(true);
  19   mmu.set_processor(this);
  20
  21   #define DECLARE_INSN(name, match, mask) \
  22     register_insn(match, mask, (insn_func_t)&processor_t::rv32_##name, (insn_func_t)&processor_t::rv64_##name);
  23   #include "opcodes.h"
  24   #undef DECLARE_INSN
  25 }
  26
  27 processor_t::~processor_t()
  28 {
  29 }
  30
  31 void processor_t::reset(bool value)
  32 {
  33   if (run == !value)
  34     return;
  35   run = !value;
  36
  37   // the ISA guarantees on boot that the PC is 0x2000 and the the processor
  38   // is in supervisor mode, and in 64-bit mode, if supported, with traps
  39   // and virtual memory disabled.
  40   sr = 0;
  41   set_pcr(PCR_SR, SR_S | SR_S64 | SR_IM);
  42   pc = 0x2000;
  43
  44   // the following state is undefined upon boot-up,
  45   // but we zero it for determinism
  46   XPR.reset();
  47   FPR.reset();
  48
  49   evec = 0;
  50   epc = 0;
  51   badvaddr = 0;
  52   cause = 0;
  53   pcr_k0 = 0;
  54   pcr_k1 = 0;
  55   count = 0;
  56   compare = 0;
  57   cycle = 0;
  58   set_fsr(0);
  59 }
  60
  61 void processor_t::set_fsr(uint32_t val)
  62 {
  63   fsr = val & ~FSR_ZERO; // clear FSR bits that read as zero
  64 }
  65
  66 void processor_t::take_interrupt()
  67 {
  68   uint32_t interrupts = (sr & SR_IP) >> SR_IP_SHIFT;
  69   interrupts &= (sr & SR_IM) >> SR_IM_SHIFT;
  70
  71   if(interrupts && (sr & SR_ET))
  72     for(int i = 0; ; i++, interrupts >>= 1)
  73       if(interrupts & 1)
  74         throw interrupt_t(i);
  75 }
  76
  77 void processor_t::step(size_t n, bool noisy)
  78 {
  79   if(!run)
  80     return;
  81
  82   size_t i = 0;
  83   try
  84   {
  85     take_interrupt();
  86
  87     mmu_t& _mmu = mmu;
  88     reg_t npc = pc;
  89
  90     // execute_insn fetches and executes one instruction
  91     #define execute_insn(noisy) \
  92       do { \
  93         mmu_t::insn_fetch_t fetch = _mmu.load_insn(npc); \
  94         if(noisy) disasm(fetch.insn, npc); \
  95         npc = fetch.func(this, fetch.insn, npc); \
  96         pc = npc; \
  97       } while(0)
  98
  99     if(noisy) for( ; i < n; i++) // print out instructions as we go
 100       execute_insn(true);
 101     else
 102     {
 103       // unrolled for speed
 104       for( ; n > 3 && i < n-3; i+=4)
 105       {
 106         execute_insn(false);
 107         execute_insn(false);
 108         execute_insn(false);
 109         execute_insn(false);
 110       }
 111       for( ; i < n; i++)
 112         execute_insn(false);
 113     }
 114   }
 115   catch(trap_t t)
 116   {
 117     // an exception occurred in the target processor
 118     take_trap(t,noisy);
 119   }
 120   catch(interrupt_t t)
 121   {
 122     take_trap((1ULL << ((sr & SR_S64) ? 63 : 31)) + t.i, noisy);
 123   }
 124
 125   cycle += i;
 126
 127   // update timer and possibly register a timer interrupt
 128   uint32_t old_count = count;
 129   count += i;
 130   if(old_count < compare && uint64_t(old_count) + i >= compare)
 131     set_interrupt(IRQ_TIMER, true);
 132 }
 133
 134 void processor_t::take_trap(reg_t t, bool noisy)
 135 {
 136   if(noisy)
 137   {
 138     if ((sreg_t)t < 0)
 139       fprintf(stderr, "core %3d: interrupt %d, epc 0x%016" PRIx64 "\n",
 140               id, uint8_t(t), pc);
 141     else
 142       fprintf(stderr, "core %3d: trap %s, epc 0x%016" PRIx64 "\n",
 143               id, trap_name(trap_t(t)), pc);
 144   }
 145
 146   // switch to supervisor, set previous supervisor bit, disable traps
 147   set_pcr(PCR_SR, (((sr & ~SR_ET) | SR_S) & ~SR_PS) | ((sr & SR_S) ? SR_PS : 0));
 148   cause = t;
 149   epc = pc;
 150   pc = evec;
 151   badvaddr = mmu.get_badvaddr();
 152 }
 153
 154 void processor_t::deliver_ipi()
 155 {
 156   if (run)
 157     set_pcr(PCR_CLR_IPI, 1);
 158 }
 159
 160 void processor_t::disasm(insn_t insn, reg_t pc)
 161 {
 162   // the disassembler is stateless, so we share it
 163   static disassembler disasm;
 164   fprintf(stderr, "core %3d: 0x%016" PRIx64 " (0x%08" PRIxFAST32 ") %s\n",
 165           id, pc, insn.bits, disasm.disassemble(insn).c_str());
 166 }
 167
 168 void processor_t::set_pcr(int which, reg_t val)
 169 {
 170   switch (which)
 171   {
 172     case PCR_SR:
 173       sr = (val & ~SR_IP) | (sr & SR_IP);
 174 #ifndef RISCV_ENABLE_64BIT
 175       sr &= ~(SR_S64 | SR_U64);
 176 #endif
 177 #ifndef RISCV_ENABLE_FPU
 178       sr &= ~SR_EF;
 179 #endif
 180 #ifndef RISCV_ENABLE_RVC
 181       sr &= ~SR_EC;
 182 #endif
 183 #ifndef RISCV_ENABLE_VEC
 184       sr &= ~SR_EV;
 185 #endif
 186       sr &= ~SR_ZERO;
 187       mmu.flush_tlb();
 188       break;
 189     case PCR_EPC:
 190       epc = val;
 191       break;
 192     case PCR_EVEC:
 193       evec = val;
 194       break;
 195     case PCR_COUNT:
 196       count = val;
 197       break;
 198     case PCR_COMPARE:
 199       set_interrupt(IRQ_TIMER, false);
 200       compare = val;
 201       break;
 202     case PCR_PTBR:
 203       mmu.set_ptbr(val);
 204       break;
 205     case PCR_SEND_IPI:
 206       sim.send_ipi(val);
 207       break;
 208     case PCR_CLR_IPI:
 209       set_interrupt(IRQ_IPI, val & 1);
 210       break;
 211     case PCR_K0:
 212       pcr_k0 = val;
 213       break;
 214     case PCR_K1:
 215       pcr_k1 = val;
 216       break;
 217     case PCR_TOHOST:
 218       if (tohost == 0)
 219         tohost = val;
 220       break;
 221     case PCR_FROMHOST:
 222       set_interrupt(IRQ_HOST, val != 0);
 223       fromhost = val;
 224       break;
 225   }
 226 }
 227
 228 reg_t processor_t::get_pcr(int which)
 229 {
 230   switch (which)
 231   {
 232     case PCR_SR:
 233       return sr;
 234     case PCR_EPC:
 235       return epc;
 236     case PCR_BADVADDR:
 237       return badvaddr;
 238     case PCR_EVEC:
 239       return evec;
 240     case PCR_COUNT:
 241       return count;
 242     case PCR_COMPARE:
 243       return compare;
 244     case PCR_CAUSE:
 245       return cause;
 246     case PCR_PTBR:
 247       return mmu.get_ptbr();
 248     case PCR_COREID:
 249       return id;
 250     case PCR_IMPL:
 251       return 1;
 252     case PCR_K0:
 253       return pcr_k0;
 254     case PCR_K1:
 255       return pcr_k1;
 256     case PCR_TOHOST:
 257       return tohost;
 258     case PCR_FROMHOST:
 259       return fromhost;
 260   }
 261   return -1;
 262 }
 263
 264 void processor_t::set_interrupt(int which, bool on)
 265 {
 266   uint32_t mask = (1 << (which + SR_IP_SHIFT)) & SR_IP;
 267   if (on)
 268     sr |= mask;
 269   else
 270     sr &= ~mask;
 271 }
 272
 273 insn_func_t processor_t::decode_insn(insn_t insn)
 274 {
 275   bool rv64 = (sr & SR_S) ? (sr & SR_S64) : (sr & SR_U64);
 276
 277   auto key = insn.bits & ((1L << opcode_bits)-1);
 278   auto it = opcode_map.find(key);
 279   for (auto it = opcode_map.find(key); it != opcode_map.end() && it->first == key; ++it)
 280     if ((insn.bits & it->second.mask) == it->second.match)
 281       return rv64 ? it->second.rv64 : it->second.rv32;
 282
 283   return &processor_t::illegal_instruction;
 284 }
 285
 286 reg_t processor_t::illegal_instruction(insn_t insn, reg_t pc)
 287 {
 288   throw trap_illegal_instruction;
 289 }
 290
 291 void processor_t::register_insn(uint32_t match, uint32_t mask, insn_func_t rv32, insn_func_t rv64)
 292 {
 293   assert(mask & 1);
 294   if (opcode_bits == 0 || (mask & ((1L << opcode_bits)-1)) != ((1L << opcode_bits)-1))
 295   {
 296     unsigned x = 0;
 297     while ((mask & ((1L << (x+1))-1)) == ((1L << (x+1))-1) &&
 298            (opcode_bits == 0 || x <= opcode_bits))
 299       x++;
 300     opcode_bits = x;
 301
 302     decltype(opcode_map) new_map;
 303     for (auto it = opcode_map.begin(); it != opcode_map.end(); ++it)
 304       new_map.insert(std::make_pair(it->second.match & ((1L<<x)-1), it->second));
 305     opcode_map = new_map;
 306   }
 307
 308   opcode_map.insert(std::make_pair(match & ((1L<<opcode_bits)-1),
 309     (opcode_map_entry_t){match, mask, rv32, rv64}));
 310 }