riscv/processor.cc

   1 #include "processor.h"
   2 #include "common.h"
   3 #include "config.h"
   4 #include "sim.h"
   5 #include "disasm.h"
   6 #include <cmath>
   7 #include <cstdlib>
   8 #include <iostream>
   9 #include <assert.h>
  10
  11 processor_t::processor_t(sim_t* _sim, mmu_t* _mmu, uint32_t _id)
  12   : sim(*_sim), mmu(*_mmu), id(_id), utidx(0)
  13 {
  14   reset();
  15
  16   // create microthreads
  17   for (int i=0; i<MAX_UTS; i++)
  18     uts[i] = new processor_t(&sim, &mmu, id, i);
  19 }
  20
  21 processor_t::processor_t(sim_t* _sim, mmu_t* _mmu, uint32_t _id,
  22                          uint32_t _utidx)
  23   : sim(*_sim), mmu(*_mmu), id(_id)
  24 {
  25   reset();
  26   set_pcr(PCR_SR, sr | SR_EF | SR_EV);
  27   utidx = _utidx;
  28
  29   // microthreads don't possess their own microthreads
  30   for (int i=0; i<MAX_UTS; i++)
  31     uts[i] = NULL;
  32 }
  33
  34 processor_t::~processor_t()
  35 {
  36 }
  37
  38 void processor_t::reset()
  39 {
  40   run = false;
  41
  42   // the ISA guarantees on boot that the PC is 0x2000 and the the processor
  43   // is in supervisor mode, and in 64-bit mode, if supported, with traps
  44   // and virtual memory disabled.  we accomplish this by setting EVEC to
  45   // 0x2000 and *enabling* traps, then sending the core an IPI.
  46   set_pcr(PCR_SR, SR_S | SR_S64 | SR_ET | SR_IM);
  47   evec = 0x2000;
  48
  49   // the following state is undefined upon boot-up,
  50   // but we zero it for determinism
  51   XPR.reset();
  52   FPR.reset();
  53
  54   pc = 0;
  55   epc = 0;
  56   badvaddr = 0;
  57   cause = 0;
  58   pcr_k0 = 0;
  59   pcr_k1 = 0;
  60   count = 0;
  61   compare = 0;
  62   cycle = 0;
  63   set_fsr(0);
  64
  65   // vector stuff
  66   vecbanks = 0xff;
  67   vecbanks_count = 8;
  68   utidx = -1;
  69   vlmax = 32;
  70   vl = 0;
  71   nxfpr_bank = 256;
  72   nxpr_use = 32;
  73   nfpr_use = 32;
  74 }
  75
  76 void processor_t::set_fsr(uint32_t val)
  77 {
  78   fsr = val & ~FSR_ZERO; // clear FSR bits that read as zero
  79 }
  80
  81 void processor_t::vcfg()
  82 {
  83   if (nxpr_use + nfpr_use < 2)
  84     vlmax = nxfpr_bank * vecbanks_count;
  85   else
  86     vlmax = (nxfpr_bank / (nxpr_use + nfpr_use - 1)) * vecbanks_count;
  87
  88   vlmax = std::min(vlmax, MAX_UTS);
  89 }
  90
  91 void processor_t::setvl(int vlapp)
  92 {
  93   vl = std::min(vlmax, vlapp);
  94 }
  95
  96 void processor_t::take_interrupt()
  97 {
  98   uint32_t interrupts = interrupts_pending;
  99   interrupts &= (sr & SR_IM) >> SR_IM_SHIFT;
 100
 101   if(interrupts && (sr & SR_ET))
 102     for(int i = 0; ; i++, interrupts >>= 1)
 103       if(interrupts & 1)
 104         throw interrupt_t(i);
 105 }
 106
 107 void processor_t::step(size_t n, bool noisy)
 108 {
 109   if(!run)
 110     return;
 111
 112   size_t i = 0;
 113   while(1) try
 114   {
 115     take_interrupt();
 116
 117     mmu_t& _mmu = mmu;
 118     insn_t insn;
 119     insn_func_t func;
 120     reg_t npc = pc;
 121
 122     // execute_insn fetches and executes one instruction
 123     #define execute_insn(noisy) \
 124       do { \
 125         insn = _mmu.load_insn(npc, sr & SR_EC, &func); \
 126         if(noisy) disasm(insn,pc); \
 127         npc = func(this, insn, npc); \
 128         pc = npc; \
 129       } while(0)
 130
 131     if(noisy) for( ; i < n; i++) // print out instructions as we go
 132       execute_insn(true);
 133     else
 134     {
 135       // unrolled for speed
 136       for( ; n > 3 && i < n-3; i+=4)
 137       {
 138         execute_insn(false);
 139         execute_insn(false);
 140         execute_insn(false);
 141         execute_insn(false);
 142       }
 143       for( ; i < n; i++)
 144         execute_insn(false);
 145     }
 146
 147     break;
 148   }
 149   catch(trap_t t)
 150   {
 151     // an exception occurred in the target processor
 152     i++;
 153     take_trap(t,noisy);
 154   }
 155   catch(interrupt_t t)
 156   {
 157     i++;
 158     take_trap((1ULL << (8*sizeof(reg_t)-1)) + t.i, noisy);
 159   }
 160   catch(vt_command_t cmd)
 161   {
 162     // this microthread has finished
 163     i++;
 164     assert(cmd == vt_command_stop);
 165     break;
 166   }
 167   catch(halt_t t)
 168   {
 169     // sleep until IPI
 170     reset();
 171     return;
 172   }
 173
 174   cycle += i;
 175
 176   // update timer and possibly register a timer interrupt
 177   uint32_t old_count = count;
 178   count += i;
 179   if(old_count < compare && uint64_t(old_count) + i >= compare)
 180     interrupts_pending |= 1 << IRQ_TIMER;
 181 }
 182
 183 void processor_t::take_trap(reg_t t, bool noisy)
 184 {
 185   if(noisy)
 186     printf("core %3d: trap %s, pc 0x%016llx\n",
 187            id, trap_name(trap_t(t)), (unsigned long long)pc);
 188
 189   // switch to supervisor, set previous supervisor bit, disable traps
 190   set_pcr(PCR_SR, (((sr & ~SR_ET) | SR_S) & ~SR_PS) | ((sr & SR_S) ? SR_PS : 0));
 191   cause = t;
 192   epc = pc;
 193   pc = evec;
 194   badvaddr = mmu.get_badvaddr();
 195 }
 196
 197 void processor_t::deliver_ipi()
 198 {
 199   interrupts_pending |= 1 << IRQ_IPI;
 200   run = true;
 201 }
 202
 203 void processor_t::disasm(insn_t insn, reg_t pc)
 204 {
 205   // the disassembler is stateless, so we share it
 206   static disassembler disasm;
 207   printf("core %3d: 0x%016llx (0x%08x) %s\n", id, (unsigned long long)pc,
 208          insn.bits, disasm.disassemble(insn).c_str());
 209 }
 210
 211 void processor_t::set_pcr(int which, reg_t val)
 212 {
 213   switch (which)
 214   {
 215     case PCR_SR:
 216       sr = val & ~SR_ZERO; // clear SR bits that read as zero
 217 #ifndef RISCV_ENABLE_64BIT
 218       sr &= ~(SR_S64 | SR_U64);
 219 #endif
 220 #ifndef RISCV_ENABLE_FPU
 221       sr &= ~SR_EF;
 222 #endif
 223 #ifndef RISCV_ENABLE_RVC
 224       sr &= ~SR_EC;
 225 #endif
 226 #ifndef RISCV_ENABLE_VEC
 227       sr &= ~SR_EV;
 228 #endif
 229       // update MMU state and flush TLB
 230       mmu.set_vm_enabled(sr & SR_VM);
 231       mmu.set_supervisor(sr & SR_S);
 232       mmu.flush_tlb();
 233       // set the fixed-point register length
 234       xprlen = ((sr & SR_S) ? (sr & SR_S64) : (sr & SR_U64)) ? 64 : 32;
 235       break;
 236     case PCR_EPC:
 237       epc = val;
 238       break;
 239     case PCR_EVEC:
 240       evec = val;
 241       break;
 242     case PCR_COUNT:
 243       count = val;
 244       break;
 245     case PCR_COMPARE:
 246       interrupts_pending &= ~(1 << IRQ_TIMER);
 247       compare = val;
 248       break;
 249     case PCR_PTBR:
 250       mmu.set_ptbr(val);
 251       break;
 252     case PCR_SEND_IPI:
 253       sim.send_ipi(val);
 254       break;
 255     case PCR_CLR_IPI:
 256       interrupts_pending &= ~(1 << IRQ_IPI);
 257       break;
 258     case PCR_K0:
 259       pcr_k0 = val;
 260       break;
 261     case PCR_K1:
 262       pcr_k1 = val;
 263       break;
 264     case PCR_VECBANK:
 265       vecbanks = val & 0xff;
 266       vecbanks_count = __builtin_popcountll(vecbanks);
 267       break;
 268     case PCR_TOHOST:
 269       sim.set_tohost(val);
 270       break;
 271   }
 272 }
 273
 274 reg_t processor_t::get_pcr(int which)
 275 {
 276   switch (which)
 277   {
 278     case PCR_SR:
 279       return sr;
 280     case PCR_EPC:
 281       return epc;
 282     case PCR_BADVADDR:
 283       return badvaddr;
 284     case PCR_EVEC:
 285       return evec;
 286     case PCR_COUNT:
 287       return count;
 288     case PCR_COMPARE:
 289       return compare;
 290     case PCR_CAUSE:
 291       return cause;
 292     case PCR_PTBR:
 293       return mmu.get_ptbr();
 294     case PCR_COREID:
 295       return id;
 296     case PCR_IMPL:
 297       return 1;
 298     case PCR_K0:
 299       return pcr_k0;
 300     case PCR_K1:
 301       return pcr_k1;
 302     case PCR_VECBANK:
 303       return vecbanks;
 304     case PCR_TOHOST:
 305       return sim.get_tohost();
 306     case PCR_FROMHOST:
 307       return sim.get_fromhost();
 308   }
 309   return -1;
 310 }