riscv/processor.cc

   1 // See LICENSE for license details.
   2
   3 #include "processor.h"
   4 #include "extension.h"
   5 #include "common.h"
   6 #include "config.h"
   7 #include "simif.h"
   8 #include "mmu.h"
   9 #include "disasm.h"
  10 #include <cinttypes>
  11 #include <cmath>
  12 #include <cstdlib>
  13 #include <iostream>
  14 #include <assert.h>
  15 #include <limits.h>
  16 #include <stdexcept>
  17 #include <algorithm>
  18 #ifdef SPIKE_SIMPLEV
  19 #include "sv_insn_redirect.h"
  20 #endif
  21
  22 #undef STATE
  23 #define STATE state
  24
  25 processor_t::processor_t(const char* isa, simif_t* sim, uint32_t id,
  26         bool halt_on_reset)
  27   : debug(false), halt_request(false), sim(sim), ext(NULL), id(id),
  28   halt_on_reset(halt_on_reset), last_pc(1), executions(1)
  29 #ifdef SPIKE_SIMPLEV
  30     , s(this)
  31 #endif
  32 {
  33   parse_isa_string(isa);
  34   register_base_instructions();
  35
  36 #ifdef SPIKE_SIMPLEV
  37   mmu = new sv_mmu_t(sim, this);
  38 #else
  39   mmu = new mmu_t(sim, this);
  40 #endif
  41
  42   disassembler = new disassembler_t(max_xlen);
  43   if (ext)
  44     for (auto disasm_insn : ext->get_disasms())
  45       disassembler->add_insn(disasm_insn);
  46
  47   reset();
  48 }
  49
  50 processor_t::~processor_t()
  51 {
  52 #ifdef RISCV_ENABLE_HISTOGRAM
  53   if (histogram_enabled)
  54   {
  55     fprintf(stderr, "PC Histogram size:%zu\n", pc_histogram.size());
  56     for (auto it : pc_histogram)
  57       fprintf(stderr, "%0" PRIx64 " %" PRIu64 "\n", it.first, it.second);
  58   }
  59 #endif
  60
  61   delete mmu;
  62   delete disassembler;
  63 }
  64
  65 static void bad_isa_string(const char* isa)
  66 {
  67   fprintf(stderr, "error: bad --isa option %s\n", isa);
  68   abort();
  69 }
  70
  71 void processor_t::parse_isa_string(const char* str)
  72 {
  73   std::string lowercase, tmp;
  74   for (const char *r = str; *r; r++)
  75     lowercase += std::tolower(*r);
  76
  77   const char* p = lowercase.c_str();
  78   const char* all_subsets = "imafdqc";
  79
  80   max_xlen = 64;
  81   state.misa = reg_t(2) << 62;
  82
  83   if (strncmp(p, "rv32", 4) == 0)
  84     max_xlen = 32, state.misa = reg_t(1) << 30, p += 4;
  85   else if (strncmp(p, "rv64", 4) == 0)
  86     p += 4;
  87   else if (strncmp(p, "rv", 2) == 0)
  88     p += 2;
  89
  90   if (!*p) {
  91     p = "imafdc";
  92   } else if (*p == 'g') { // treat "G" as "IMAFD"
  93     tmp = std::string("imafd") + (p+1);
  94     p = &tmp[0];
  95   } else if (*p != 'i') {
  96     bad_isa_string(str);
  97   }
  98
  99   isa_string = "rv" + std::to_string(max_xlen) + p;
 100   state.misa |= 1L << ('s' - 'a'); // advertise support for supervisor mode
 101   state.misa |= 1L << ('u' - 'a'); // advertise support for user mode
 102
 103   while (*p) {
 104     state.misa |= 1L << (*p - 'a');
 105
 106     if (auto next = strchr(all_subsets, *p)) {
 107       all_subsets = next + 1;
 108       p++;
 109     } else if (*p == 'x') {
 110       const char* ext = p+1, *end = ext;
 111       while (islower(*end))
 112         end++;
 113       register_extension(find_extension(std::string(ext, end - ext).c_str())());
 114       p = end;
 115     } else {
 116       bad_isa_string(str);
 117     }
 118   }
 119
 120   if (supports_extension('D') && !supports_extension('F'))
 121     bad_isa_string(str);
 122
 123   if (supports_extension('Q') && !supports_extension('D'))
 124     bad_isa_string(str);
 125
 126   if (supports_extension('Q') && max_xlen < 64)
 127     bad_isa_string(str);
 128
 129   max_isa = state.misa;
 130 }
 131
 132 void state_t::reset(reg_t max_isa)
 133 {
 134   memset(this, 0, sizeof(*this));
 135   misa = max_isa;
 136   prv = PRV_M;
 137   pc = DEFAULT_RSTVEC;
 138   tselect = 0;
 139   for (unsigned int i = 0; i < num_triggers; i++)
 140     mcontrol[i].type = 2;
 141 }
 142
 143 int state_t::sv_csr_sz()
 144 {
 145     if (prv == PRV_M)
 146         return SV_MCSR_SZ;
 147     if (prv == PRV_S)
 148         return SV_SCSR_SZ;
 149     return SV_UCSR_SZ;
 150 }
 151 sv_csr_t &state_t::sv()
 152 {
 153     if (prv == PRV_M)
 154         return get_msv();
 155     if (prv == PRV_S)
 156         return get_ssv();
 157     return get_usv();
 158 }
 159
 160 sv_shape_t* state_t::get_shape(reg_t reg)
 161 {
 162     if (prv == PRV_M || prv == PRV_S || reg == 0) {
 163         return NULL;
 164     }
 165     for (int i = 0; i < 3; i++) {
 166         if (remap[i].regidx == reg) {
 167             return &shape[i];
 168         }
 169     }
 170     return NULL;
 171 }
 172
 173 void processor_t::set_debug(bool value)
 174 {
 175   debug = value;
 176   if (ext)
 177     ext->set_debug(value);
 178 }
 179
 180 void processor_t::set_histogram(bool value)
 181 {
 182   histogram_enabled = value;
 183 #ifndef RISCV_ENABLE_HISTOGRAM
 184   if (value) {
 185     fprintf(stderr, "PC Histogram support has not been properly enabled;");
 186     fprintf(stderr, " please re-build the riscv-isa-run project using \"configure --enable-histogram\".\n");
 187   }
 188 #endif
 189 }
 190
 191 void processor_t::reset()
 192 {
 193   state.reset(max_isa);
 194   state.dcsr.halt = halt_on_reset;
 195   halt_on_reset = false;
 196   set_csr(CSR_MSTATUS, state.mstatus);
 197
 198   if (ext)
 199     ext->reset(); // reset the extension
 200
 201   if (sim)
 202     sim->proc_reset(id);
 203 }
 204
 205 // Count number of contiguous 0 bits starting from the LSB.
 206 static int ctz(reg_t val)
 207 {
 208   int res = 0;
 209   if (val)
 210     while ((val & 1) == 0)
 211       val >>= 1, res++;
 212   return res;
 213 }
 214
 215 void processor_t::take_interrupt(reg_t pending_interrupts)
 216 {
 217   reg_t mie = get_field(state.mstatus, MSTATUS_MIE);
 218   reg_t m_enabled = state.prv < PRV_M || (state.prv == PRV_M && mie);
 219   reg_t enabled_interrupts = pending_interrupts & ~state.mideleg & -m_enabled;
 220
 221   reg_t sie = get_field(state.mstatus, MSTATUS_SIE);
 222   reg_t s_enabled = state.prv < PRV_S || (state.prv == PRV_S && sie);
 223   // M-ints have highest priority; consider S-ints only if no M-ints pending
 224   if (enabled_interrupts == 0)
 225     enabled_interrupts = pending_interrupts & state.mideleg & -s_enabled;
 226
 227   if (state.dcsr.cause == 0 && enabled_interrupts) {
 228     // nonstandard interrupts have highest priority
 229     if (enabled_interrupts >> IRQ_M_EXT)
 230       enabled_interrupts = enabled_interrupts >> IRQ_M_EXT << IRQ_M_EXT;
 231     // external interrupts have next-highest priority
 232     else if (enabled_interrupts & (MIP_MEIP | MIP_SEIP))
 233       enabled_interrupts = enabled_interrupts & (MIP_MEIP | MIP_SEIP);
 234     // software interrupts have next-highest priority
 235     else if (enabled_interrupts & (MIP_MSIP | MIP_SSIP))
 236       enabled_interrupts = enabled_interrupts & (MIP_MSIP | MIP_SSIP);
 237     // timer interrupts have next-highest priority
 238     else if (enabled_interrupts & (MIP_MTIP | MIP_STIP))
 239       enabled_interrupts = enabled_interrupts & (MIP_MTIP | MIP_STIP);
 240     else
 241       abort();
 242
 243     throw trap_t(((reg_t)1 << (max_xlen-1)) | ctz(enabled_interrupts));
 244   }
 245 }
 246
 247 static int xlen_to_uxl(int xlen)
 248 {
 249   if (xlen == 32)
 250     return 1;
 251   if (xlen == 64)
 252     return 2;
 253   abort();
 254 }
 255
 256 reg_t processor_t::legalize_privilege(reg_t prv)
 257 {
 258   assert(prv <= PRV_M);
 259
 260   if (!supports_extension('U'))
 261     return PRV_M;
 262
 263   if (prv == PRV_H || !supports_extension('S'))
 264     return PRV_U;
 265
 266   return prv;
 267 }
 268
 269 void processor_t::set_privilege(reg_t prv)
 270 {
 271   mmu->flush_tlb();
 272   state.prv = legalize_privilege(prv);
 273 }
 274
 275 void processor_t::enter_debug_mode(uint8_t cause)
 276 {
 277   state.dcsr.cause = cause;
 278   state.dcsr.prv = state.prv;
 279   set_privilege(PRV_M);
 280   state.dpc = state.pc;
 281   state.pc = DEBUG_ROM_ENTRY;
 282 }
 283
 284 void processor_t::take_trap(trap_t& t, reg_t epc)
 285 {
 286   if (debug) {
 287     fprintf(stderr, "core %3d: exception %s, epc 0x%016" PRIx64 "\n",
 288             id, t.name(), epc);
 289     if (t.has_tval())
 290       fprintf(stderr, "core %3d:           tval 0x%016" PRIx64 "\n", id,
 291           t.get_tval());
 292   }
 293
 294   if (state.dcsr.cause) {
 295     if (t.cause() == CAUSE_BREAKPOINT) {
 296       state.pc = DEBUG_ROM_ENTRY;
 297     } else {
 298       state.pc = DEBUG_ROM_TVEC;
 299     }
 300     return;
 301   }
 302
 303   if (t.cause() == CAUSE_BREAKPOINT && (
 304               (state.prv == PRV_M && state.dcsr.ebreakm) ||
 305               (state.prv == PRV_S && state.dcsr.ebreaks) ||
 306               (state.prv == PRV_U && state.dcsr.ebreaku))) {
 307     enter_debug_mode(DCSR_CAUSE_SWBP);
 308     return;
 309   }
 310
 311   // by default, trap to M-mode, unless delegated to S-mode
 312   reg_t bit = t.cause();
 313   reg_t deleg = state.medeleg;
 314   bool interrupt = (bit & ((reg_t)1 << (max_xlen-1))) != 0;
 315   if (interrupt)
 316     deleg = state.mideleg, bit &= ~((reg_t)1 << (max_xlen-1));
 317   if (state.prv <= PRV_S && bit < max_xlen && ((deleg >> bit) & 1)) {
 318     // handle the trap in S-mode
 319     state.pc = state.stvec;
 320     state.scause = t.cause();
 321     state.sepc = epc;
 322     state.stval = t.get_tval();
 323
 324     reg_t s = state.mstatus;
 325     s = set_field(s, MSTATUS_SPIE, get_field(s, MSTATUS_SIE));
 326     s = set_field(s, MSTATUS_SPP, state.prv);
 327     s = set_field(s, MSTATUS_SIE, 0);
 328     set_csr(CSR_MSTATUS, s);
 329     set_privilege(PRV_S);
 330   } else {
 331     reg_t vector = (state.mtvec & 1) && interrupt ? 4*bit : 0;
 332     state.pc = (state.mtvec & ~(reg_t)1) + vector;
 333     state.mepc = epc;
 334     state.mcause = t.cause();
 335     state.mtval = t.get_tval();
 336
 337     reg_t s = state.mstatus;
 338     s = set_field(s, MSTATUS_MPIE, get_field(s, MSTATUS_MIE));
 339     s = set_field(s, MSTATUS_MPP, state.prv);
 340     s = set_field(s, MSTATUS_MIE, 0);
 341     set_csr(CSR_MSTATUS, s);
 342     set_privilege(PRV_M);
 343   }
 344 }
 345
 346 void processor_t::disasm(insn_t insn)
 347 {
 348   uint64_t bits = insn.bits() & ((1ULL << (8 * insn_length(insn.bits()))) - 1);
 349   if (last_pc != state.pc || last_bits != bits) {
 350     if (executions != 1) {
 351       fprintf(stderr, "core %3d: Executed %" PRIx64 " times\n", id, executions);
 352     }
 353
 354     fprintf(stderr, "core %3d: 0x%016" PRIx64 " (0x%08" PRIx64 ") %s\n",
 355             id, state.pc, bits, disassembler->disassemble(insn).c_str());
 356     last_pc = state.pc;
 357     last_bits = bits;
 358     executions = 1;
 359   } else {
 360     executions++;
 361   }
 362 }
 363
 364 int processor_t::paddr_bits()
 365 {
 366   assert(xlen == max_xlen);
 367   return max_xlen == 64 ? 50 : 34;
 368 }
 369
 370 void processor_t::set_csr(int which, reg_t val)
 371 {
 372   val = _zext_xlen(val);
 373   reg_t delegable_ints = MIP_SSIP | MIP_STIP | MIP_SEIP
 374                        | ((ext != NULL) << IRQ_COP);
 375   reg_t all_ints = delegable_ints | MIP_MSIP | MIP_MTIP;
 376   fprintf(stderr, "set CSR %x %lx\n", which, val);
 377   switch (which)
 378   {
 379 #ifdef SPIKE_SIMPLEV
 380     case CSR_USVMVL:
 381       state.sv().mvl = std::min(val, (uint64_t)64); // limited to XLEN width
 382       // TODO XXX throw exception if val == 0
 383       fprintf(stderr, "set MVL %lx\n", state.sv().mvl);
 384       break;
 385     case CSR_USVSTATE:
 386       // bits 0-5: mvl - 6-11: vl - 12-17: srcoffs - 18-23: destoffs
 387       set_csr(CSR_USVMVL, get_field(val, 0x1f   )+1);
 388       set_csr(CSR_USVVL , get_field(val, 0x1f<<6)+1);
 389       state.sv().srcoffs  = std::min(get_field(val, 0x1f<<12), state.sv().vl-1);
 390       state.sv().destoffs = std::min(get_field(val, 0x1f<<18), state.sv().vl-1);
 391       break;
 392     case CSR_USVVL:
 393       state.sv().vl = std::min(state.sv().mvl, val);
 394       // TODO XXX throw exception if val == 0
 395       fprintf(stderr, "set VL %lx\n", state.sv().vl);
 396       break;
 397     case CSR_SVREGCFG0:
 398     case CSR_SVREGCFG1:
 399     case CSR_SVREGCFG2:
 400     case CSR_SVREGCFG3:
 401     case CSR_SVREGCFG4:
 402     case CSR_SVREGCFG5:
 403     case CSR_SVREGCFG6:
 404     case CSR_SVREGCFG7:
 405     {
 406       uint64_t v = (uint64_t)val;
 407       // identify which (pair) of SV config CAM registers are being set
 408       int tbidx = (which - CSR_SVREGCFG0) * 2;
 409       fprintf(stderr, "set REGCFG %d %lx\n", tbidx, v);
 410       // lower 16 bits go into even, upper into odd...
 411       state.sv().sv_csrs[tbidx].u = get_field(v, 0xffffUL);
 412       state.sv().sv_csrs[tbidx+1].u = get_field(v, 0xffffUL<<16);
 413       int clroffset = 2;
 414       if (xlen == 64)
 415       {
 416           state.sv().sv_csrs[tbidx+2].u = get_field(v, 0xffffUL<<32);
 417           state.sv().sv_csrs[tbidx+3].u = get_field(v, 0xffffUL<<48);
 418         clroffset = 4;
 419       }
 420       // clear out all CSRs above the one(s) being set: this ensures that
 421       // when it comes to context-switching, it's clear what needs to be saved
 422       for (int i = tbidx+clroffset; i < 16; i++)
 423       {
 424           fprintf(stderr, "clr REGCFG %d\n", i);
 425           state.sv().sv_csrs[i].u = 0;
 426       }
 427       // okaaay and now "unpack" the CAM to make it easier to use.  this
 428       // approach is not designed to be efficient right now.  optimise later
 429       // first clear the old tables
 430       memset(state.sv().sv_int_tb, 0, sizeof(state.sv().sv_int_tb));
 431       memset(state.sv().sv_fp_tb, 0, sizeof(state.sv().sv_fp_tb));
 432       // now walk the CAM and unpack it
 433       for (int i = 0; i < state.sv_csr_sz(); i++)
 434       {
 435         union sv_reg_csr_entry *c = &state.sv().sv_csrs[i];
 436         uint64_t idx = c->b.regkey;
 437         sv_reg_entry *r;
 438         if (c->u == 0)
 439         {
 440             break;
 441         }
 442         // XXX damn.  this basically duplicates sv_insn_t::get_regentry.
 443         if (c->b.type == 1)
 444         {
 445             r = &state.sv().sv_int_tb[idx];
 446         }
 447         else
 448         {
 449             r = &state.sv().sv_fp_tb[idx];
 450         }
 451         r->elwidth = c->b.elwidth;
 452         r->regidx = c->b.regidx;
 453         r->isvec = c->b.isvec;
 454         r->active = true;
 455         fprintf(stderr, "setting REGCFG type:%d isvec:%d %d %d\n",
 456                         c->b.type, r->isvec, (int)idx, (int)r->regidx);
 457       }
 458       break;
 459     }
 460     case CSR_SVPREDCFG0:
 461     case CSR_SVPREDCFG1:
 462     case CSR_SVPREDCFG2:
 463     case CSR_SVPREDCFG3:
 464     case CSR_SVPREDCFG4:
 465     case CSR_SVPREDCFG5:
 466     case CSR_SVPREDCFG6:
 467     case CSR_SVPREDCFG7:
 468     {
 469       // comments removed as it's near-identical to the regs version
 470       // TODO: macro-ify
 471       uint64_t v = (uint64_t)val;
 472       int tbidx = (which - CSR_SVPREDCFG0) * 2;
 473       fprintf(stderr, "set PREDCFG %d %lx\n", tbidx, v);
 474       state.sv().sv_pred_csrs[tbidx].u = get_field(v, 0xffff);
 475       state.sv().sv_pred_csrs[tbidx+1].u = get_field(v, 0xffff0000);
 476       int clroffset = 2;
 477       if (xlen == 64)
 478       {
 479           state.sv().sv_pred_csrs[tbidx+2].u = get_field(v, 0xffffUL<<32);
 480           state.sv().sv_pred_csrs[tbidx+3].u = get_field(v, 0xffffUL<<48);
 481           clroffset = 4;
 482       }
 483       for (int i = tbidx+clroffset; i < 16; i++)
 484       {
 485           state.sv().sv_pred_csrs[i].u = 0;
 486       }
 487       memset(state.sv().sv_pred_int_tb, 0, sizeof(state.sv().sv_pred_int_tb));
 488       memset(state.sv().sv_pred_fp_tb, 0, sizeof(state.sv().sv_pred_fp_tb));
 489       for (int i = 0; i < state.sv_csr_sz(); i++)
 490       {
 491         union sv_pred_csr_entry *c = &state.sv().sv_pred_csrs[i];
 492         uint64_t idx = c->b.regkey;
 493         if (c->u == 0)
 494         {
 495             break;
 496         }
 497         sv_pred_entry *r;
 498         // XXX damn.  this basically duplicates sv_insn_t::get_predentry.
 499         if (c->b.type == 1)
 500         {
 501             r = &state.sv().sv_pred_int_tb[idx];
 502         }
 503         else
 504         {
 505             r = &state.sv().sv_pred_fp_tb[idx];
 506         }
 507         r->regidx = c->b.regidx;
 508         r->zero   = c->b.zero;
 509         r->inv    = c->b.inv;
 510         r->packed = c->b.packed;
 511         r->active = true;
 512         fprintf(stderr, "setting PREDCFG %d type:%d zero:%d %d %d\n",
 513                         i, c->b.type, r->zero, (int)idx, (int)r->regidx);
 514       }
 515       break;
 516     }
 517 #endif
 518     case CSR_FFLAGS:
 519       dirty_fp_state;
 520       state.fflags = val & (FSR_AEXC >> FSR_AEXC_SHIFT);
 521       break;
 522     case CSR_FRM:
 523       dirty_fp_state;
 524       state.frm = val & (FSR_RD >> FSR_RD_SHIFT);
 525       break;
 526     case CSR_FCSR:
 527       dirty_fp_state;
 528       state.fflags = (val & FSR_AEXC) >> FSR_AEXC_SHIFT;
 529       state.frm = (val & FSR_RD) >> FSR_RD_SHIFT;
 530       break;
 531     case CSR_MSTATUS: {
 532       if ((val ^ state.mstatus) &
 533           (MSTATUS_MPP | MSTATUS_MPRV | MSTATUS_SUM | MSTATUS_MXR))
 534         mmu->flush_tlb();
 535
 536       reg_t mask = MSTATUS_SIE | MSTATUS_SPIE | MSTATUS_MIE | MSTATUS_MPIE
 537                  | MSTATUS_FS | MSTATUS_MPRV | MSTATUS_SUM
 538                  | MSTATUS_MXR | MSTATUS_TW | MSTATUS_TVM
 539                  | MSTATUS_TSR | MSTATUS_UXL | MSTATUS_SXL |
 540                  (ext ? MSTATUS_XS : 0);
 541
 542       reg_t requested_mpp = legalize_privilege(get_field(val, MSTATUS_MPP));
 543       state.mstatus = set_field(state.mstatus, MSTATUS_MPP, requested_mpp);
 544       if (supports_extension('S'))
 545         mask |= MSTATUS_SPP;
 546
 547       state.mstatus = (state.mstatus & ~mask) | (val & mask);
 548
 549       bool dirty = (state.mstatus & MSTATUS_FS) == MSTATUS_FS;
 550       dirty |= (state.mstatus & MSTATUS_XS) == MSTATUS_XS;
 551       if (max_xlen == 32)
 552         state.mstatus = set_field(state.mstatus, MSTATUS32_SD, dirty);
 553       else
 554         state.mstatus = set_field(state.mstatus, MSTATUS64_SD, dirty);
 555
 556       state.mstatus = set_field(state.mstatus, MSTATUS_UXL, xlen_to_uxl(max_xlen));
 557       state.mstatus = set_field(state.mstatus, MSTATUS_UXL, xlen_to_uxl(max_xlen));
 558       state.mstatus = set_field(state.mstatus, MSTATUS_SXL, xlen_to_uxl(max_xlen));
 559       // U-XLEN == S-XLEN == M-XLEN
 560       xlen = max_xlen;
 561       break;
 562     }
 563     case CSR_MIP: {
 564       reg_t mask = MIP_SSIP | MIP_STIP;
 565       state.mip = (state.mip & ~mask) | (val & mask);
 566       break;
 567     }
 568     case CSR_MIE:
 569       state.mie = (state.mie & ~all_ints) | (val & all_ints);
 570       break;
 571     case CSR_MIDELEG:
 572       state.mideleg = (state.mideleg & ~delegable_ints) | (val & delegable_ints);
 573       break;
 574     case CSR_MEDELEG: {
 575       reg_t mask =
 576         (1 << CAUSE_MISALIGNED_FETCH) |
 577         (1 << CAUSE_BREAKPOINT) |
 578         (1 << CAUSE_USER_ECALL) |
 579         (1 << CAUSE_FETCH_PAGE_FAULT) |
 580         (1 << CAUSE_LOAD_PAGE_FAULT) |
 581         (1 << CAUSE_STORE_PAGE_FAULT);
 582       state.medeleg = (state.medeleg & ~mask) | (val & mask);
 583       break;
 584     }
 585     case CSR_MINSTRET:
 586     case CSR_MCYCLE:
 587       if (xlen == 32)
 588         state.minstret = (state.minstret >> 32 << 32) | (val & 0xffffffffU);
 589       else
 590         state.minstret = val;
 591       // The ISA mandates that if an instruction writes instret, the write
 592       // takes precedence over the increment to instret.  However, Spike
 593       // unconditionally increments instret after executing an instruction.
 594       // Correct for this artifact by decrementing instret here.
 595       state.minstret--;
 596       break;
 597     case CSR_MINSTRETH:
 598     case CSR_MCYCLEH:
 599       state.minstret = (val << 32) | (state.minstret << 32 >> 32);
 600       state.minstret--; // See comment above.
 601       break;
 602     case CSR_SCOUNTEREN:
 603       state.scounteren = val;
 604       break;
 605     case CSR_MCOUNTEREN:
 606       state.mcounteren = val;
 607       break;
 608     case CSR_SSTATUS: {
 609       reg_t mask = SSTATUS_SIE | SSTATUS_SPIE | SSTATUS_SPP | SSTATUS_FS
 610                  | SSTATUS_XS | SSTATUS_SUM | SSTATUS_MXR;
 611       return set_csr(CSR_MSTATUS, (state.mstatus & ~mask) | (val & mask));
 612     }
 613     case CSR_SIP: {
 614       reg_t mask = MIP_SSIP & state.mideleg;
 615       return set_csr(CSR_MIP, (state.mip & ~mask) | (val & mask));
 616     }
 617     case CSR_SIE:
 618       return set_csr(CSR_MIE,
 619                      (state.mie & ~state.mideleg) | (val & state.mideleg));
 620     case CSR_SATP: {
 621       mmu->flush_tlb();
 622       if (max_xlen == 32)
 623         state.satp = val & (SATP32_PPN | SATP32_MODE);
 624       if (max_xlen == 64 && (get_field(val, SATP64_MODE) == SATP_MODE_OFF ||
 625                              get_field(val, SATP64_MODE) == SATP_MODE_SV39 ||
 626                              get_field(val, SATP64_MODE) == SATP_MODE_SV48))
 627         state.satp = val & (SATP64_PPN | SATP64_MODE);
 628       break;
 629     }
 630     case CSR_SEPC: state.sepc = val & ~(reg_t)1; break;
 631     case CSR_STVEC: state.stvec = val >> 2 << 2; break;
 632     case CSR_SSCRATCH: state.sscratch = val; break;
 633     case CSR_SCAUSE: state.scause = val; break;
 634     case CSR_STVAL: state.stval = val; break;
 635     case CSR_MEPC: state.mepc = val & ~(reg_t)1; break;
 636     case CSR_MTVEC: state.mtvec = val & ~(reg_t)2; break;
 637     case CSR_MSCRATCH: state.mscratch = val; break;
 638     case CSR_MCAUSE: state.mcause = val; break;
 639     case CSR_MTVAL: state.mtval = val; break;
 640     case CSR_MISA: {
 641       // the write is ignored if increasing IALIGN would misalign the PC
 642       if (!(val & (1L << ('C' - 'A'))) && (state.pc & 2))
 643         break;
 644
 645       if (!(val & (1L << ('F' - 'A'))))
 646         val &= ~(1L << ('D' - 'A'));
 647
 648       // allow MAFDC bits in MISA to be modified
 649       reg_t mask = 0;
 650       mask |= 1L << ('M' - 'A');
 651       mask |= 1L << ('A' - 'A');
 652       mask |= 1L << ('F' - 'A');
 653       mask |= 1L << ('D' - 'A');
 654       mask |= 1L << ('C' - 'A');
 655       mask &= max_isa;
 656
 657       state.misa = (val & mask) | (state.misa & ~mask);
 658       break;
 659     }
 660     case CSR_TSELECT:
 661       if (val < state.num_triggers) {
 662         state.tselect = val;
 663       }
 664       break;
 665     case CSR_TDATA1:
 666       {
 667         mcontrol_t *mc = &state.mcontrol[state.tselect];
 668         if (mc->dmode && !state.dcsr.cause) {
 669           break;
 670         }
 671         mc->dmode = get_field(val, MCONTROL_DMODE(xlen));
 672         mc->select = get_field(val, MCONTROL_SELECT);
 673         mc->timing = get_field(val, MCONTROL_TIMING);
 674         mc->action = (mcontrol_action_t) get_field(val, MCONTROL_ACTION);
 675         mc->chain = get_field(val, MCONTROL_CHAIN);
 676         mc->match = (mcontrol_match_t) get_field(val, MCONTROL_MATCH);
 677         mc->m = get_field(val, MCONTROL_M);
 678         mc->h = get_field(val, MCONTROL_H);
 679         mc->s = get_field(val, MCONTROL_S);
 680         mc->u = get_field(val, MCONTROL_U);
 681         mc->execute = get_field(val, MCONTROL_EXECUTE);
 682         mc->store = get_field(val, MCONTROL_STORE);
 683         mc->load = get_field(val, MCONTROL_LOAD);
 684         // Assume we're here because of csrw.
 685         if (mc->execute)
 686           mc->timing = 0;
 687         trigger_updated();
 688       }
 689       break;
 690     case CSR_TDATA2:
 691       if (state.mcontrol[state.tselect].dmode && !state.dcsr.cause) {
 692         break;
 693       }
 694       if (state.tselect < state.num_triggers) {
 695         state.tdata2[state.tselect] = val;
 696       }
 697       break;
 698     case CSR_DCSR:
 699       state.dcsr.prv = get_field(val, DCSR_PRV);
 700       state.dcsr.step = get_field(val, DCSR_STEP);
 701       // TODO: ndreset and fullreset
 702       state.dcsr.ebreakm = get_field(val, DCSR_EBREAKM);
 703       state.dcsr.ebreakh = get_field(val, DCSR_EBREAKH);
 704       state.dcsr.ebreaks = get_field(val, DCSR_EBREAKS);
 705       state.dcsr.ebreaku = get_field(val, DCSR_EBREAKU);
 706       state.dcsr.halt = get_field(val, DCSR_HALT);
 707       break;
 708     case CSR_DPC:
 709       state.dpc = val & ~(reg_t)1;
 710       break;
 711     case CSR_DSCRATCH:
 712       state.dscratch = val;
 713       break;
 714   }
 715 }
 716
 717 reg_t processor_t::get_csr(int which)
 718 {
 719   uint32_t ctr_en = -1;
 720   if (state.prv < PRV_M)
 721     ctr_en &= state.mcounteren;
 722   if (state.prv < PRV_S)
 723     ctr_en &= state.scounteren;
 724   bool ctr_ok = (ctr_en >> (which & 31)) & 1;
 725
 726   if (ctr_ok) {
 727     if (which >= CSR_HPMCOUNTER3 && which <= CSR_HPMCOUNTER31)
 728       return 0;
 729     if (xlen == 32 && which >= CSR_HPMCOUNTER3H && which <= CSR_HPMCOUNTER31H)
 730       return 0;
 731   }
 732   if (which >= CSR_MHPMCOUNTER3 && which <= CSR_MHPMCOUNTER31)
 733     return 0;
 734   if (xlen == 32 && which >= CSR_MHPMCOUNTER3H && which <= CSR_MHPMCOUNTER31H)
 735     return 0;
 736   if (which >= CSR_MHPMEVENT3 && which <= CSR_MHPMEVENT31)
 737     return 0;
 738
 739   switch (which)
 740   {
 741 #ifdef SPIKE_SIMPLEV
 742     case CSR_USVVL:
 743       return state.sv().vl;
 744     case CSR_USVSTATE:
 745       return (state.sv().vl-1)            | ((state.sv().mvl-1)<<6) |
 746              (state.sv().srcoffs<<12)     | (state.sv().destoffs<<18) ;
 747     case CSR_USVMVL:
 748       return state.sv().mvl;
 749     case CSR_SVREGCFG0:
 750     case CSR_SVREGCFG1:
 751     case CSR_SVREGCFG2:
 752     case CSR_SVREGCFG3:
 753     case CSR_SVREGCFG4:
 754     case CSR_SVREGCFG5:
 755     case CSR_SVREGCFG6:
 756     case CSR_SVREGCFG7:
 757       return 0;// XXX TODO: return correct entry
 758     case CSR_SVPREDCFG0:
 759     case CSR_SVPREDCFG1:
 760     case CSR_SVPREDCFG2:
 761     case CSR_SVPREDCFG3:
 762     case CSR_SVPREDCFG4:
 763     case CSR_SVPREDCFG5:
 764     case CSR_SVPREDCFG6:
 765     case CSR_SVPREDCFG7:
 766       return 0;// XXX TODO: return correct entry
 767 #endif
 768     case CSR_FFLAGS:
 769       require_fp;
 770       if (!supports_extension('F'))
 771         break;
 772       return state.fflags;
 773     case CSR_FRM:
 774       require_fp;
 775       if (!supports_extension('F'))
 776         break;
 777       return state.frm;
 778     case CSR_FCSR:
 779       require_fp;
 780       if (!supports_extension('F'))
 781         break;
 782       return (state.fflags << FSR_AEXC_SHIFT) | (state.frm << FSR_RD_SHIFT);
 783     case CSR_INSTRET:
 784     case CSR_CYCLE:
 785       if (ctr_ok)
 786         return state.minstret;
 787       break;
 788     case CSR_MINSTRET:
 789     case CSR_MCYCLE:
 790       return state.minstret;
 791     case CSR_INSTRETH:
 792     case CSR_CYCLEH:
 793       if (ctr_ok && xlen == 32)
 794         return state.minstret >> 32;
 795       break;
 796     case CSR_MINSTRETH:
 797     case CSR_MCYCLEH:
 798       if (xlen == 32)
 799         return state.minstret >> 32;
 800       break;
 801     case CSR_SCOUNTEREN: return state.scounteren;
 802     case CSR_MCOUNTEREN: return state.mcounteren;
 803     case CSR_SSTATUS: {
 804       reg_t mask = SSTATUS_SIE | SSTATUS_SPIE | SSTATUS_SPP | SSTATUS_FS
 805                  | SSTATUS_XS | SSTATUS_SUM | SSTATUS_MXR | SSTATUS_UXL;
 806       reg_t sstatus = state.mstatus & mask;
 807       if ((sstatus & SSTATUS_FS) == SSTATUS_FS ||
 808           (sstatus & SSTATUS_XS) == SSTATUS_XS)
 809         sstatus |= (xlen == 32 ? SSTATUS32_SD : SSTATUS64_SD);
 810       return sstatus;
 811     }
 812     case CSR_SIP: return state.mip & state.mideleg;
 813     case CSR_SIE: return state.mie & state.mideleg;
 814     case CSR_SEPC: return state.sepc & pc_alignment_mask();
 815     case CSR_STVAL: return state.stval;
 816     case CSR_STVEC: return state.stvec;
 817     case CSR_SCAUSE:
 818       if (max_xlen > xlen)
 819         return state.scause | ((state.scause >> (max_xlen-1)) << (xlen-1));
 820       return state.scause;
 821     case CSR_SATP:
 822       if (get_field(state.mstatus, MSTATUS_TVM))
 823         require_privilege(PRV_M);
 824       return state.satp;
 825     case CSR_SSCRATCH: return state.sscratch;
 826     case CSR_MSTATUS: return state.mstatus;
 827     case CSR_MIP: return state.mip;
 828     case CSR_MIE: return state.mie;
 829     case CSR_MEPC: return state.mepc & pc_alignment_mask();
 830     case CSR_MSCRATCH: return state.mscratch;
 831     case CSR_MCAUSE: return state.mcause;
 832     case CSR_MTVAL: return state.mtval;
 833     case CSR_MISA: return state.misa;
 834     case CSR_MARCHID: return 0;
 835     case CSR_MIMPID: return 0;
 836     case CSR_MVENDORID: return 0;
 837     case CSR_MHARTID: return id;
 838     case CSR_MTVEC: return state.mtvec;
 839     case CSR_MEDELEG: return state.medeleg;
 840     case CSR_MIDELEG: return state.mideleg;
 841     case CSR_TSELECT: return state.tselect;
 842     case CSR_TDATA1:
 843       if (state.tselect < state.num_triggers) {
 844         reg_t v = 0;
 845         mcontrol_t *mc = &state.mcontrol[state.tselect];
 846         v = set_field(v, MCONTROL_TYPE(xlen), mc->type);
 847         v = set_field(v, MCONTROL_DMODE(xlen), mc->dmode);
 848         v = set_field(v, MCONTROL_MASKMAX(xlen), mc->maskmax);
 849         v = set_field(v, MCONTROL_SELECT, mc->select);
 850         v = set_field(v, MCONTROL_TIMING, mc->timing);
 851         v = set_field(v, MCONTROL_ACTION, mc->action);
 852         v = set_field(v, MCONTROL_CHAIN, mc->chain);
 853         v = set_field(v, MCONTROL_MATCH, mc->match);
 854         v = set_field(v, MCONTROL_M, mc->m);
 855         v = set_field(v, MCONTROL_H, mc->h);
 856         v = set_field(v, MCONTROL_S, mc->s);
 857         v = set_field(v, MCONTROL_U, mc->u);
 858         v = set_field(v, MCONTROL_EXECUTE, mc->execute);
 859         v = set_field(v, MCONTROL_STORE, mc->store);
 860         v = set_field(v, MCONTROL_LOAD, mc->load);
 861         return v;
 862       } else {
 863         return 0;
 864       }
 865       break;
 866     case CSR_TDATA2:
 867       if (state.tselect < state.num_triggers) {
 868         return state.tdata2[state.tselect];
 869       } else {
 870         return 0;
 871       }
 872       break;
 873     case CSR_TDATA3: return 0;
 874     case CSR_DCSR:
 875       {
 876         uint32_t v = 0;
 877         v = set_field(v, DCSR_XDEBUGVER, 1);
 878         v = set_field(v, DCSR_EBREAKM, state.dcsr.ebreakm);
 879         v = set_field(v, DCSR_EBREAKH, state.dcsr.ebreakh);
 880         v = set_field(v, DCSR_EBREAKS, state.dcsr.ebreaks);
 881         v = set_field(v, DCSR_EBREAKU, state.dcsr.ebreaku);
 882         v = set_field(v, DCSR_STOPCYCLE, 0);
 883         v = set_field(v, DCSR_STOPTIME, 0);
 884         v = set_field(v, DCSR_CAUSE, state.dcsr.cause);
 885         v = set_field(v, DCSR_STEP, state.dcsr.step);
 886         v = set_field(v, DCSR_PRV, state.dcsr.prv);
 887         return v;
 888       }
 889     case CSR_DPC:
 890       return state.dpc & pc_alignment_mask();
 891     case CSR_DSCRATCH:
 892       return state.dscratch;
 893   }
 894   throw trap_illegal_instruction(0);
 895 }
 896
 897 reg_t illegal_instruction(processor_t* p, insn_t insn, reg_t pc)
 898 {
 899   throw trap_illegal_instruction(0);
 900 }
 901
 902 insn_func_t processor_t::decode_insn(insn_t insn)
 903 {
 904   // look up opcode in hash table
 905   size_t idx = insn.bits() % OPCODE_CACHE_SIZE;
 906   insn_desc_t desc = opcode_cache[idx];
 907
 908   if (unlikely(insn.bits() != desc.match)) {
 909     // fall back to linear search
 910     insn_desc_t* p = &instructions[0];
 911     while ((insn.bits() & p->mask) != p->match)
 912       p++;
 913     desc = *p;
 914
 915     if (p->mask != 0 && p > &instructions[0]) {
 916       if (p->match != (p-1)->match && p->match != (p+1)->match) {
 917         // move to front of opcode list to reduce miss penalty
 918         while (--p >= &instructions[0])
 919           *(p+1) = *p;
 920         instructions[0] = desc;
 921       }
 922     }
 923
 924     opcode_cache[idx] = desc;
 925     opcode_cache[idx].match = insn.bits();
 926   }
 927
 928   return xlen == 64 ? desc.rv64 : desc.rv32;
 929 }
 930
 931 void processor_t::register_insn(insn_desc_t desc)
 932 {
 933   instructions.push_back(desc);
 934 }
 935
 936 void processor_t::build_opcode_map()
 937 {
 938   struct cmp {
 939     bool operator()(const insn_desc_t& lhs, const insn_desc_t& rhs) {
 940       if (lhs.match == rhs.match)
 941         return lhs.mask > rhs.mask;
 942       return lhs.match > rhs.match;
 943     }
 944   };
 945   std::sort(instructions.begin(), instructions.end(), cmp());
 946
 947   for (size_t i = 0; i < OPCODE_CACHE_SIZE; i++)
 948     opcode_cache[i] = {0, 0, &illegal_instruction, &illegal_instruction};
 949 }
 950
 951 void processor_t::register_extension(extension_t* x)
 952 {
 953   for (auto insn : x->get_instructions())
 954     register_insn(insn);
 955   build_opcode_map();
 956   for (auto disasm_insn : x->get_disasms())
 957     disassembler->add_insn(disasm_insn);
 958   if (ext != NULL)
 959     throw std::logic_error("only one extension may be registered");
 960   ext = x;
 961   x->set_processor(this);
 962 }
 963
 964 void processor_t::register_base_instructions()
 965 {
 966   #define DECLARE_INSN(name, match, mask) \
 967     insn_bits_t name##_match = (match), name##_mask = (mask);
 968   #include "encoding.h"
 969   #undef DECLARE_INSN
 970
 971   #define DEFINE_INSN(name) \
 972     REGISTER_INSN(this, name, name##_match, name##_mask)
 973   #include "insn_list.h"
 974   #undef DEFINE_INSN
 975
 976   register_insn({0, 0, &illegal_instruction, &illegal_instruction});
 977   build_opcode_map();
 978 }
 979
 980 bool processor_t::load(reg_t addr, size_t len, uint8_t* bytes)
 981 {
 982   switch (addr)
 983   {
 984     case 0:
 985       if (len <= 4) {
 986         memset(bytes, 0, len);
 987         bytes[0] = get_field(state.mip, MIP_MSIP);
 988         return true;
 989       }
 990       break;
 991   }
 992
 993   return false;
 994 }
 995
 996 bool processor_t::store(reg_t addr, size_t len, const uint8_t* bytes)
 997 {
 998   switch (addr)
 999   {
1000     case 0:
1001       if (len <= 4) {
1002         state.mip = set_field(state.mip, MIP_MSIP, bytes[0]);
1003         return true;
1004       }
1005       break;
1006   }
1007
1008   return false;
1009 }
1010
1011 void processor_t::trigger_updated()
1012 {
1013   mmu->flush_tlb();
1014   mmu->check_triggers_fetch = false;
1015   mmu->check_triggers_load = false;
1016   mmu->check_triggers_store = false;
1017
1018   for (unsigned i = 0; i < state.num_triggers; i++) {
1019     if (state.mcontrol[i].execute) {
1020       mmu->check_triggers_fetch = true;
1021     }
1022     if (state.mcontrol[i].load) {
1023       mmu->check_triggers_load = true;
1024     }
1025     if (state.mcontrol[i].store) {
1026       mmu->check_triggers_store = true;
1027     }
1028   }
1029 }
1030