riscv/processor.cc

   1 // See LICENSE for license details.
   2
   3 #include "processor.h"
   4 #include "extension.h"
   5 #include "common.h"
   6 #include "config.h"
   7 #include "sim.h"
   8 #include "disasm.h"
   9 #include <cinttypes>
  10 #include <cmath>
  11 #include <cstdlib>
  12 #include <iostream>
  13 #include <assert.h>
  14 #include <limits.h>
  15 #include <stdexcept>
  16
  17 processor_t::processor_t(sim_t* _sim, mmu_t* _mmu, uint32_t _id)
  18   : sim(_sim), mmu(_mmu), ext(NULL), id(_id), debug(false), opcode_bits(0)
  19 {
  20   reset(true);
  21   mmu->set_processor(this);
  22
  23   #define DECLARE_INSN(name, match, mask) REGISTER_INSN(this, name, match, mask)
  24   #include "opcodes.h"
  25   #undef DECLARE_INSN
  26 }
  27
  28 processor_t::~processor_t()
  29 {
  30 }
  31
  32 void state_t::reset()
  33 {
  34   // the ISA guarantees on boot that the PC is 0x2000 and the the processor
  35   // is in supervisor mode, and in 64-bit mode, if supported, with traps
  36   // and virtual memory disabled.
  37   sr = SR_S;
  38 #ifdef RISCV_ENABLE_64BIT
  39   sr |= SR_S64;
  40 #endif
  41   pc = 0x2000;
  42
  43   // the following state is undefined upon boot-up,
  44   // but we zero it for determinism
  45   XPR.reset();
  46   FPR.reset();
  47
  48   evec = 0;
  49   epc = 0;
  50   badvaddr = 0;
  51   cause = 0;
  52   pcr_k0 = 0;
  53   pcr_k1 = 0;
  54   count = 0;
  55   compare = 0;
  56   cycle = 0;
  57   fsr = 0;
  58
  59   load_reservation = -1;
  60 }
  61
  62 void processor_t::set_debug(bool value)
  63 {
  64   debug = value;
  65   if (ext)
  66     ext->set_debug(value);
  67 }
  68
  69 void processor_t::reset(bool value)
  70 {
  71   if (run == !value)
  72     return;
  73   run = !value;
  74
  75   state.reset(); // reset the core
  76   if (ext)
  77     ext->reset(); // reset the extension
  78 }
  79
  80 uint32_t processor_t::set_fsr(uint32_t val)
  81 {
  82   uint32_t old_fsr = state.fsr;
  83   state.fsr = val & ~FSR_ZERO; // clear FSR bits that read as zero
  84   return old_fsr;
  85 }
  86
  87 void processor_t::take_interrupt()
  88 {
  89   uint32_t interrupts = (state.sr & SR_IP) >> SR_IP_SHIFT;
  90   interrupts &= (state.sr & SR_IM) >> SR_IM_SHIFT;
  91
  92   if (interrupts && (state.sr & SR_EI))
  93     for (int i = 0; ; i++, interrupts >>= 1)
  94       if (interrupts & 1)
  95         throw trap_t((1ULL << ((state.sr & SR_S64) ? 63 : 31)) + i);
  96 }
  97
  98 void processor_t::step(size_t n)
  99 {
 100   if(!run)
 101     return;
 102
 103   size_t i = 0;
 104   reg_t npc = state.pc;
 105   mmu_t* _mmu = mmu;
 106
 107   try
 108   {
 109     take_interrupt();
 110
 111     // execute_insn fetches and executes one instruction
 112     #define execute_insn(noisy) \
 113       do { \
 114         mmu_t::insn_fetch_t fetch = _mmu->load_insn(npc); \
 115         if(noisy) disasm(fetch.insn.insn); \
 116         npc = fetch.func(this, fetch.insn.insn, npc); \
 117       } while(0)
 118
 119
 120     // special execute_insn  for commit log dumping
 121 #ifdef RISCV_ENABLE_COMMITLOG
 122     //static disassembler disasmblr;
 123     #undef execute_insn
 124     #define execute_insn(noisy) \
 125       do { \
 126         mmu_t::insn_fetch_t fetch = _mmu->load_insn(npc); \
 127         if(noisy) disasm(fetch.insn.insn); \
 128         bool in_spvr = state.sr & SR_S; \
 129         if (!in_spvr) fprintf(stderr, "\n0x%016" PRIx64 " (0x%08" PRIx32 ") ", npc, fetch.insn.insn.bits()); \
 130         /*if (!in_spvr) fprintf(stderr, "\n0x%016" PRIx64 " (0x%08" PRIx32 ") %s  ", npc, fetch.insn.insn.bits(), disasmblr.disassemble(fetch.insn.insn).c_str());*/ \
 131         npc = fetch.func(this, fetch.insn.insn, npc); \
 132       } while(0)
 133 #endif
 134
 135     if(debug) for( ; i < n; i++) // print out instructions as we go
 136       execute_insn(true);
 137     else
 138     {
 139       // unrolled for speed
 140       for( ; n > 3 && i < n-3; i+=4)
 141       {
 142         execute_insn(false);
 143         execute_insn(false);
 144         execute_insn(false);
 145         execute_insn(false);
 146       }
 147       for( ; i < n; i++)
 148         execute_insn(false);
 149     }
 150
 151     state.pc = npc;
 152   }
 153   catch(trap_t& t)
 154   {
 155     take_trap(npc, t);
 156   }
 157
 158   state.cycle += i;
 159
 160   // update timer and possibly register a timer interrupt
 161   uint32_t old_count = state.count;
 162   state.count += i;
 163   if(old_count < state.compare && uint64_t(old_count) + i >= state.compare)
 164     set_interrupt(IRQ_TIMER, true);
 165 }
 166
 167 void processor_t::take_trap(reg_t pc, trap_t& t)
 168 {
 169   if (debug)
 170     fprintf(stderr, "core %3d: exception %s, epc 0x%016" PRIx64 "\n",
 171             id, t.name(), pc);
 172
 173   // switch to supervisor, set previous supervisor bit, disable interrupts
 174   set_pcr(PCR_SR, (((state.sr & ~SR_EI) | SR_S) & ~SR_PS & ~SR_PEI) |
 175                   ((state.sr & SR_S) ? SR_PS : 0) |
 176                   ((state.sr & SR_EI) ? SR_PEI : 0));
 177
 178   yield_load_reservation();
 179   state.cause = t.cause();
 180   state.epc = pc;
 181   state.pc = state.evec;
 182
 183   t.side_effects(&state); // might set badvaddr etc.
 184 }
 185
 186 void processor_t::deliver_ipi()
 187 {
 188   if (run)
 189     set_pcr(PCR_CLR_IPI, 1);
 190 }
 191
 192 void processor_t::disasm(insn_t insn)
 193 {
 194   // the disassembler is stateless, so we share it
 195   fprintf(stderr, "core %3d: 0x%016" PRIx64 " (0x%08" PRIx32 ") %s\n",
 196           id, state.pc, insn.bits(), disassembler.disassemble(insn).c_str());
 197 }
 198
 199 reg_t processor_t::set_pcr(int which, reg_t val)
 200 {
 201   reg_t old_pcr = get_pcr(which);
 202
 203   switch (which)
 204   {
 205     case PCR_SR:
 206       state.sr = (val & ~SR_IP) | (state.sr & SR_IP);
 207 #ifndef RISCV_ENABLE_64BIT
 208       state.sr &= ~(SR_S64 | SR_U64);
 209 #endif
 210 #ifndef RISCV_ENABLE_FPU
 211       state.sr &= ~SR_EF;
 212 #endif
 213       if (!ext)
 214         state.sr &= ~SR_EA;
 215       state.sr &= ~SR_ZERO;
 216       mmu->flush_tlb();
 217       break;
 218     case PCR_EPC:
 219       state.epc = val;
 220       break;
 221     case PCR_EVEC:
 222       state.evec = val;
 223       break;
 224     case PCR_COUNT:
 225       state.count = val;
 226       break;
 227     case PCR_COMPARE:
 228       set_interrupt(IRQ_TIMER, false);
 229       state.compare = val;
 230       break;
 231     case PCR_PTBR:
 232       state.ptbr = val & ~(PGSIZE-1);
 233       break;
 234     case PCR_SEND_IPI:
 235       sim->send_ipi(val);
 236       break;
 237     case PCR_CLR_IPI:
 238       set_interrupt(IRQ_IPI, val & 1);
 239       break;
 240     case PCR_SUP0:
 241       state.pcr_k0 = val;
 242       break;
 243     case PCR_SUP1:
 244       state.pcr_k1 = val;
 245       break;
 246     case PCR_TOHOST:
 247       if (state.tohost == 0)
 248         state.tohost = val;
 249       break;
 250     case PCR_FROMHOST:
 251       set_interrupt(IRQ_HOST, val != 0);
 252       state.fromhost = val;
 253       break;
 254   }
 255
 256   return old_pcr;
 257 }
 258
 259 reg_t processor_t::get_pcr(int which)
 260 {
 261   switch (which)
 262   {
 263     case PCR_SR:
 264       return state.sr;
 265     case PCR_EPC:
 266       return state.epc;
 267     case PCR_BADVADDR:
 268       return state.badvaddr;
 269     case PCR_EVEC:
 270       return state.evec;
 271     case PCR_COUNT:
 272       return state.count;
 273     case PCR_COMPARE:
 274       return state.compare;
 275     case PCR_CAUSE:
 276       return state.cause;
 277     case PCR_PTBR:
 278       return state.ptbr;
 279     case PCR_ASID:
 280       return 0;
 281     case PCR_FATC:
 282       mmu->flush_tlb();
 283       return 0;
 284     case PCR_HARTID:
 285       return id;
 286     case PCR_IMPL:
 287       return 1;
 288     case PCR_SUP0:
 289       return state.pcr_k0;
 290     case PCR_SUP1:
 291       return state.pcr_k1;
 292     case PCR_TOHOST:
 293       return state.tohost;
 294     case PCR_FROMHOST:
 295       return state.fromhost;
 296   }
 297   return -1;
 298 }
 299
 300 void processor_t::set_interrupt(int which, bool on)
 301 {
 302   uint32_t mask = (1 << (which + SR_IP_SHIFT)) & SR_IP;
 303   if (on)
 304     state.sr |= mask;
 305   else
 306     state.sr &= ~mask;
 307 }
 308
 309 reg_t illegal_instruction(processor_t* p, insn_t insn, reg_t pc)
 310 {
 311   throw trap_illegal_instruction();
 312 }
 313
 314 insn_func_t processor_t::decode_insn(insn_t insn)
 315 {
 316   bool rv64 = (state.sr & SR_S) ? (state.sr & SR_S64) : (state.sr & SR_U64);
 317
 318   auto key = insn.bits() & ((1L << opcode_bits)-1);
 319   for (auto it = opcode_map.find(key); it != opcode_map.end() && it->first == key; ++it)
 320     if ((insn.bits() & it->second.mask) == it->second.match)
 321       return rv64 ? it->second.rv64 : it->second.rv32;
 322
 323   return &illegal_instruction;
 324 }
 325
 326 void processor_t::register_insn(insn_desc_t desc)
 327 {
 328   assert(desc.mask & 1);
 329   if (opcode_bits == 0 || (desc.mask & ((1L << opcode_bits)-1)) != ((1L << opcode_bits)-1))
 330   {
 331     unsigned x = 0;
 332     while ((desc.mask & ((1L << (x+1))-1)) == ((1L << (x+1))-1) &&
 333            (opcode_bits == 0 || x <= opcode_bits))
 334       x++;
 335     opcode_bits = x;
 336
 337     decltype(opcode_map) new_map;
 338     for (auto it = opcode_map.begin(); it != opcode_map.end(); ++it)
 339       new_map.insert(std::make_pair(it->second.match & ((1L<<x)-1), it->second));
 340     opcode_map = new_map;
 341   }
 342
 343   opcode_map.insert(std::make_pair(desc.match & ((1L<<opcode_bits)-1), desc));
 344 }
 345
 346 void processor_t::register_extension(extension_t* x)
 347 {
 348   for (auto insn : x->get_instructions())
 349     register_insn(insn);
 350   for (auto disasm_insn : x->get_disasms())
 351     disassembler.add_insn(disasm_insn);
 352   if (ext != NULL)
 353     throw std::logic_error("only one extension may be registered");
 354   ext = x;
 355   x->set_processor(this);
 356 }