riscv/processor.cc

   1 // See LICENSE for license details.
   2
   3 #include "processor.h"
   4 #include "extension.h"
   5 #include "common.h"
   6 #include "config.h"
   7 #include "sim.h"
   8 #include "htif.h"
   9 #include "disasm.h"
  10 #include <cinttypes>
  11 #include <cmath>
  12 #include <cstdlib>
  13 #include <iostream>
  14 #include <assert.h>
  15 #include <limits.h>
  16 #include <stdexcept>
  17 #include <algorithm>
  18
  19 #undef STATE
  20 #define STATE state
  21
  22 processor_t::processor_t(const char* isa, sim_t* sim, uint32_t id)
  23   : sim(sim), ext(NULL), disassembler(new disassembler_t),
  24     id(id), run(false), debug(false)
  25 {
  26   parse_isa_string(isa);
  27
  28   mmu = new mmu_t(sim->mem, sim->memsz);
  29   mmu->set_processor(this);
  30
  31   reset(true);
  32
  33   register_base_instructions();
  34 }
  35
  36 processor_t::~processor_t()
  37 {
  38 #ifdef RISCV_ENABLE_HISTOGRAM
  39   if (histogram_enabled)
  40   {
  41     fprintf(stderr, "PC Histogram size:%zu\n", pc_histogram.size());
  42     for (auto it : pc_histogram)
  43       fprintf(stderr, "%0" PRIx64 " %" PRIu64 "\n", it.first, it.second);
  44   }
  45 #endif
  46
  47   delete mmu;
  48   delete disassembler;
  49 }
  50
  51 static void bad_isa_string(const char* isa)
  52 {
  53   fprintf(stderr, "error: bad --isa option %s\n", isa);
  54   abort();
  55 }
  56
  57 void processor_t::parse_isa_string(const char* str)
  58 {
  59   std::string lowercase, tmp;
  60   for (const char *r = str; *r; r++)
  61     lowercase += std::tolower(*r);
  62
  63   const char* p = lowercase.c_str();
  64   const char* all_subsets = "imafdc";
  65
  66   max_xlen = 64;
  67   cpuid = reg_t(2) << 62;
  68
  69   if (strncmp(p, "rv32", 4) == 0)
  70     max_xlen = 32, cpuid = 0, p += 4;
  71   else if (strncmp(p, "rv64", 4) == 0)
  72     p += 4;
  73   else if (strncmp(p, "rv", 2) == 0)
  74     p += 2;
  75
  76   if (!*p) {
  77     p = all_subsets;
  78   } else if (*p == 'g') { // treat "G" as "IMAFD"
  79     tmp = std::string("imafd") + (p+1);
  80     p = &tmp[0];
  81   } else if (*p != 'i') {
  82     bad_isa_string(str);
  83   }
  84
  85   isa = "rv" + std::to_string(max_xlen) + p;
  86   cpuid |= 1L << ('s' - 'a'); // advertise support for supervisor mode
  87
  88   while (*p) {
  89     cpuid |= 1L << (*p - 'a');
  90
  91     if (auto next = strchr(all_subsets, *p)) {
  92       all_subsets = next + 1;
  93       p++;
  94     } else if (*p == 'x') {
  95       const char* ext = p+1, *end = ext;
  96       while (islower(*end))
  97         end++;
  98       register_extension(find_extension(std::string(ext, end - ext).c_str())());
  99       p = end;
 100     } else {
 101       bad_isa_string(str);
 102     }
 103   }
 104
 105   if (supports_extension('D') && !supports_extension('F'))
 106     bad_isa_string(str);
 107 }
 108
 109 void state_t::reset()
 110 {
 111   memset(this, 0, sizeof(*this));
 112   mstatus = set_field(mstatus, MSTATUS_PRV, PRV_M);
 113   mstatus = set_field(mstatus, MSTATUS_PRV1, PRV_U);
 114   mstatus = set_field(mstatus, MSTATUS_PRV2, PRV_U);
 115   pc = DEFAULT_MTVEC + 0x100;
 116   load_reservation = -1;
 117 }
 118
 119 void processor_t::set_debug(bool value)
 120 {
 121   debug = value;
 122   if (ext)
 123     ext->set_debug(value);
 124 }
 125
 126 void processor_t::set_histogram(bool value)
 127 {
 128   histogram_enabled = value;
 129 #ifndef RISCV_ENABLE_HISTOGRAM
 130   if (value) {
 131     fprintf(stderr, "PC Histogram support has not been properly enabled;");
 132     fprintf(stderr, " please re-build the riscv-isa-run project using \"configure --enable-histogram\".\n");
 133   }
 134 #endif
 135 }
 136
 137 void processor_t::reset(bool value)
 138 {
 139   if (run == !value)
 140     return;
 141   run = !value;
 142
 143   state.reset();
 144   set_csr(CSR_MSTATUS, state.mstatus);
 145
 146   if (ext)
 147     ext->reset(); // reset the extension
 148 }
 149
 150 void processor_t::raise_interrupt(reg_t which)
 151 {
 152   throw trap_t(((reg_t)1 << (max_xlen-1)) | which);
 153 }
 154
 155 void processor_t::take_interrupt()
 156 {
 157   int priv = get_field(state.mstatus, MSTATUS_PRV);
 158   int ie = get_field(state.mstatus, MSTATUS_IE);
 159   reg_t interrupts = state.mie & state.mip;
 160
 161   if (priv < PRV_M || (priv == PRV_M && ie)) {
 162     if (interrupts & MIP_MSIP)
 163       raise_interrupt(IRQ_SOFT);
 164
 165     if (interrupts & MIP_MTIP)
 166       raise_interrupt(IRQ_TIMER);
 167
 168     if (state.fromhost != 0)
 169       raise_interrupt(IRQ_HOST);
 170   }
 171
 172   if (priv < PRV_S || (priv == PRV_S && ie)) {
 173     if (interrupts & MIP_SSIP)
 174       raise_interrupt(IRQ_SOFT);
 175
 176     if (interrupts & MIP_STIP)
 177       raise_interrupt(IRQ_TIMER);
 178   }
 179 }
 180
 181 void processor_t::check_timer()
 182 {
 183   if (sim->rtc >= state.mtimecmp)
 184     state.mip |= MIP_MTIP;
 185 }
 186
 187 void processor_t::push_privilege_stack()
 188 {
 189   reg_t s = state.mstatus;
 190   s = set_field(s, MSTATUS_PRV2, get_field(state.mstatus, MSTATUS_PRV1));
 191   s = set_field(s, MSTATUS_IE2, get_field(state.mstatus, MSTATUS_IE1));
 192   s = set_field(s, MSTATUS_PRV1, get_field(state.mstatus, MSTATUS_PRV));
 193   s = set_field(s, MSTATUS_IE1, get_field(state.mstatus, MSTATUS_IE));
 194   s = set_field(s, MSTATUS_PRV, PRV_M);
 195   s = set_field(s, MSTATUS_MPRV, 0);
 196   s = set_field(s, MSTATUS_IE, 0);
 197   set_csr(CSR_MSTATUS, s);
 198 }
 199
 200 void processor_t::pop_privilege_stack()
 201 {
 202   reg_t s = state.mstatus;
 203   s = set_field(s, MSTATUS_PRV, get_field(state.mstatus, MSTATUS_PRV1));
 204   s = set_field(s, MSTATUS_IE, get_field(state.mstatus, MSTATUS_IE1));
 205   s = set_field(s, MSTATUS_PRV1, get_field(state.mstatus, MSTATUS_PRV2));
 206   s = set_field(s, MSTATUS_IE1, get_field(state.mstatus, MSTATUS_IE2));
 207   s = set_field(s, MSTATUS_PRV2, PRV_U);
 208   s = set_field(s, MSTATUS_IE2, 1);
 209   set_csr(CSR_MSTATUS, s);
 210 }
 211
 212 void processor_t::take_trap(trap_t& t, reg_t epc)
 213 {
 214   if (debug)
 215     fprintf(stderr, "core %3d: exception %s, epc 0x%016" PRIx64 "\n",
 216             id, t.name(), epc);
 217
 218   state.pc = DEFAULT_MTVEC + 0x40 * get_field(state.mstatus, MSTATUS_PRV);
 219   push_privilege_stack();
 220   yield_load_reservation();
 221   state.mcause = t.cause();
 222   state.mepc = epc;
 223   t.side_effects(&state); // might set badvaddr etc.
 224 }
 225
 226 void processor_t::disasm(insn_t insn)
 227 {
 228   uint64_t bits = insn.bits() & ((1ULL << (8 * insn_length(insn.bits()))) - 1);
 229   fprintf(stderr, "core %3d: 0x%016" PRIx64 " (0x%08" PRIx64 ") %s\n",
 230           id, state.pc, bits, disassembler->disassemble(insn).c_str());
 231 }
 232
 233 static bool validate_priv(reg_t priv)
 234 {
 235   return priv == PRV_U || priv == PRV_S || priv == PRV_M;
 236 }
 237
 238 static bool validate_vm(int max_xlen, reg_t vm)
 239 {
 240   if (max_xlen == 64 && (vm == VM_SV39 || vm == VM_SV48))
 241     return true;
 242   if (max_xlen == 32 && vm == VM_SV32)
 243     return true;
 244   return vm == VM_MBARE;
 245 }
 246
 247 void processor_t::set_csr(int which, reg_t val)
 248 {
 249   switch (which)
 250   {
 251     case CSR_FFLAGS:
 252       dirty_fp_state;
 253       state.fflags = val & (FSR_AEXC >> FSR_AEXC_SHIFT);
 254       break;
 255     case CSR_FRM:
 256       dirty_fp_state;
 257       state.frm = val & (FSR_RD >> FSR_RD_SHIFT);
 258       break;
 259     case CSR_FCSR:
 260       dirty_fp_state;
 261       state.fflags = (val & FSR_AEXC) >> FSR_AEXC_SHIFT;
 262       state.frm = (val & FSR_RD) >> FSR_RD_SHIFT;
 263       break;
 264     case CSR_MTIME:
 265     case CSR_STIMEW:
 266       // this implementation ignores writes to MTIME
 267       break;
 268     case CSR_MTIMEH:
 269     case CSR_STIMEHW:
 270       // this implementation ignores writes to MTIME
 271       break;
 272     case CSR_TIMEW:
 273       val -= sim->rtc;
 274       if (xlen == 32)
 275         state.sutime_delta = (uint32_t)val | (state.sutime_delta >> 32 << 32);
 276       else
 277         state.sutime_delta = val;
 278       break;
 279     case CSR_TIMEHW:
 280       val = ((val << 32) - sim->rtc) >> 32;
 281       state.sutime_delta = (val << 32) | (uint32_t)state.sutime_delta;
 282       break;
 283     case CSR_CYCLEW:
 284     case CSR_INSTRETW:
 285       val -= state.minstret;
 286       if (xlen == 32)
 287         state.suinstret_delta = (uint32_t)val | (state.suinstret_delta >> 32 << 32);
 288       else
 289         state.suinstret_delta = val;
 290       break;
 291     case CSR_CYCLEHW:
 292     case CSR_INSTRETHW:
 293       val = ((val << 32) - state.minstret) >> 32;
 294       state.suinstret_delta = (val << 32) | (uint32_t)state.suinstret_delta;
 295       break;
 296     case CSR_MSTATUS: {
 297       if ((val ^ state.mstatus) & (MSTATUS_VM | MSTATUS_PRV | MSTATUS_PRV1 | MSTATUS_MPRV))
 298         mmu->flush_tlb();
 299
 300       reg_t mask = MSTATUS_IE | MSTATUS_IE1 | MSTATUS_IE2 | MSTATUS_MPRV
 301                    | MSTATUS_FS | (ext ? MSTATUS_XS : 0);
 302
 303       if (validate_vm(max_xlen, get_field(val, MSTATUS_VM)))
 304         mask |= MSTATUS_VM;
 305       if (validate_priv(get_field(val, MSTATUS_PRV)))
 306         mask |= MSTATUS_PRV;
 307       if (validate_priv(get_field(val, MSTATUS_PRV1)))
 308         mask |= MSTATUS_PRV1;
 309       if (validate_priv(get_field(val, MSTATUS_PRV2)))
 310         mask |= MSTATUS_PRV2;
 311
 312       state.mstatus = (state.mstatus & ~mask) | (val & mask);
 313
 314       bool dirty = (state.mstatus & MSTATUS_FS) == MSTATUS_FS;
 315       dirty |= (state.mstatus & MSTATUS_XS) == MSTATUS_XS;
 316       if (max_xlen == 32)
 317         state.mstatus = set_field(state.mstatus, MSTATUS32_SD, dirty);
 318       else
 319         state.mstatus = set_field(state.mstatus, MSTATUS64_SD, dirty);
 320
 321       // spike supports the notion of xlen < max_xlen, but current priv spec
 322       // doesn't provide a mechanism to run RV32 software on an RV64 machine
 323       xlen = max_xlen;
 324       break;
 325     }
 326     case CSR_MIP: {
 327       reg_t mask = MIP_SSIP | MIP_MSIP | MIP_STIP;
 328       state.mip = (state.mip & ~mask) | (val & mask);
 329       break;
 330     }
 331     case CSR_MIPI: {
 332       state.mip |= MIP_MSIP;
 333       break;
 334     }
 335     case CSR_MIE: {
 336       reg_t mask = MIP_SSIP | MIP_MSIP | MIP_STIP | MIP_MTIP;
 337       state.mie = (state.mie & ~mask) | (val & mask);
 338       break;
 339     }
 340     case CSR_SSTATUS: {
 341       reg_t ms = state.mstatus;
 342       ms = set_field(ms, MSTATUS_IE, get_field(val, SSTATUS_IE));
 343       ms = set_field(ms, MSTATUS_IE1, get_field(val, SSTATUS_PIE));
 344       ms = set_field(ms, MSTATUS_PRV1, get_field(val, SSTATUS_PS));
 345       ms = set_field(ms, MSTATUS_FS, get_field(val, SSTATUS_FS));
 346       ms = set_field(ms, MSTATUS_XS, get_field(val, SSTATUS_XS));
 347       ms = set_field(ms, MSTATUS_MPRV, get_field(val, SSTATUS_MPRV));
 348       return set_csr(CSR_MSTATUS, ms);
 349     }
 350     case CSR_SIP: {
 351       reg_t mask = MIP_SSIP;
 352       state.mip = (state.mip & ~mask) | (val & mask);
 353       break;
 354     }
 355     case CSR_SIE: {
 356       reg_t mask = MIP_SSIP | MIP_STIP;
 357       state.mie = (state.mie & ~mask) | (val & mask);
 358       break;
 359     }
 360     case CSR_SEPC: state.sepc = val; break;
 361     case CSR_STVEC: state.stvec = val >> 2 << 2; break;
 362     case CSR_SPTBR: state.sptbr = zext_xlen(val & -PGSIZE); break;
 363     case CSR_SSCRATCH: state.sscratch = val; break;
 364     case CSR_MEPC: state.mepc = val; break;
 365     case CSR_MSCRATCH: state.mscratch = val; break;
 366     case CSR_MCAUSE: state.mcause = val; break;
 367     case CSR_MBADADDR: state.mbadaddr = val; break;
 368     case CSR_MTIMECMP:
 369       state.mip &= ~MIP_MTIP;
 370       state.mtimecmp = val;
 371       break;
 372     case CSR_MTOHOST:
 373       if (state.tohost == 0)
 374         state.tohost = val;
 375       break;
 376     case CSR_MFROMHOST: state.fromhost = val; break;
 377   }
 378 }
 379
 380 reg_t processor_t::get_csr(int which)
 381 {
 382   switch (which)
 383   {
 384     case CSR_FFLAGS:
 385       require_fp;
 386       if (!supports_extension('F'))
 387         break;
 388       return state.fflags;
 389     case CSR_FRM:
 390       require_fp;
 391       if (!supports_extension('F'))
 392         break;
 393       return state.frm;
 394     case CSR_FCSR:
 395       require_fp;
 396       if (!supports_extension('F'))
 397         break;
 398       return (state.fflags << FSR_AEXC_SHIFT) | (state.frm << FSR_RD_SHIFT);
 399     case CSR_MTIME:
 400     case CSR_STIME:
 401     case CSR_STIMEW:
 402       return sim->rtc;
 403     case CSR_MTIMEH:
 404     case CSR_STIMEH:
 405     case CSR_STIMEHW:
 406       return sim->rtc >> 32;
 407     case CSR_TIME:
 408     case CSR_TIMEW:
 409       return sim->rtc + state.sutime_delta;
 410     case CSR_CYCLE:
 411     case CSR_CYCLEW:
 412     case CSR_INSTRET:
 413     case CSR_INSTRETW:
 414       return state.minstret + state.suinstret_delta;
 415     case CSR_TIMEH:
 416     case CSR_TIMEHW:
 417       if (xlen == 64)
 418         break;
 419       return (sim->rtc + state.sutime_delta) >> 32;
 420     case CSR_CYCLEH:
 421     case CSR_INSTRETH:
 422     case CSR_CYCLEHW:
 423     case CSR_INSTRETHW:
 424       if (xlen == 64)
 425         break;
 426       return (state.minstret + state.suinstret_delta) >> 32;
 427     case CSR_SSTATUS: {
 428       reg_t ss = 0;
 429       ss = set_field(ss, SSTATUS_IE, get_field(state.mstatus, MSTATUS_IE));
 430       ss = set_field(ss, SSTATUS_PIE, get_field(state.mstatus, MSTATUS_IE1));
 431       ss = set_field(ss, SSTATUS_PS, get_field(state.mstatus, MSTATUS_PRV1));
 432       ss = set_field(ss, SSTATUS_FS, get_field(state.mstatus, MSTATUS_FS));
 433       ss = set_field(ss, SSTATUS_XS, get_field(state.mstatus, MSTATUS_XS));
 434       ss = set_field(ss, SSTATUS_MPRV, get_field(state.mstatus, MSTATUS_MPRV));
 435       if (get_field(state.mstatus, MSTATUS64_SD))
 436         ss = set_field(ss, (xlen == 32 ? SSTATUS32_SD : SSTATUS64_SD), 1);
 437       return ss;
 438     }
 439     case CSR_SIP: return state.mip & (MIP_SSIP | MIP_STIP);
 440     case CSR_SIE: return state.mie & (MIP_SSIP | MIP_STIP);
 441     case CSR_SEPC: return state.sepc;
 442     case CSR_SBADADDR: return state.sbadaddr;
 443     case CSR_STVEC: return state.stvec;
 444     case CSR_SCAUSE:
 445       if (max_xlen > xlen)
 446         return state.scause | ((state.scause >> (max_xlen-1)) << (xlen-1));
 447       return state.scause;
 448     case CSR_SPTBR: return state.sptbr;
 449     case CSR_SASID: return 0;
 450     case CSR_SSCRATCH: return state.sscratch;
 451     case CSR_MSTATUS: return state.mstatus;
 452     case CSR_MIP: return state.mip;
 453     case CSR_MIPI: return 0;
 454     case CSR_MIE: return state.mie;
 455     case CSR_MEPC: return state.mepc;
 456     case CSR_MSCRATCH: return state.mscratch;
 457     case CSR_MCAUSE: return state.mcause;
 458     case CSR_MBADADDR: return state.mbadaddr;
 459     case CSR_MTIMECMP: return state.mtimecmp;
 460     case CSR_MCPUID: return cpuid;
 461     case CSR_MIMPID: return IMPL_ROCKET;
 462     case CSR_MHARTID: return id;
 463     case CSR_MTVEC: return DEFAULT_MTVEC;
 464     case CSR_MTDELEG: return 0;
 465     case CSR_MTOHOST:
 466       sim->get_htif()->tick(); // not necessary, but faster
 467       return state.tohost;
 468     case CSR_MFROMHOST:
 469       sim->get_htif()->tick(); // not necessary, but faster
 470       return state.fromhost;
 471     case CSR_MIOBASE: return sim->memsz;
 472     case CSR_UARCH0:
 473     case CSR_UARCH1:
 474     case CSR_UARCH2:
 475     case CSR_UARCH3:
 476     case CSR_UARCH4:
 477     case CSR_UARCH5:
 478     case CSR_UARCH6:
 479     case CSR_UARCH7:
 480     case CSR_UARCH8:
 481     case CSR_UARCH9:
 482     case CSR_UARCH10:
 483     case CSR_UARCH11:
 484     case CSR_UARCH12:
 485     case CSR_UARCH13:
 486     case CSR_UARCH14:
 487     case CSR_UARCH15:
 488       return 0;
 489   }
 490   throw trap_illegal_instruction();
 491 }
 492
 493 reg_t illegal_instruction(processor_t* p, insn_t insn, reg_t pc)
 494 {
 495   throw trap_illegal_instruction();
 496 }
 497
 498 insn_func_t processor_t::decode_insn(insn_t insn)
 499 {
 500   // look up opcode in hash table
 501   size_t idx = insn.bits() % OPCODE_CACHE_SIZE;
 502   insn_desc_t desc = opcode_cache[idx];
 503
 504   if (unlikely(insn.bits() != desc.match)) {
 505     // fall back to linear search
 506     insn_desc_t* p = &instructions[0];
 507     while ((insn.bits() & p->mask) != p->match)
 508       p++;
 509     desc = *p;
 510
 511     if (p->mask != 0 && p > &instructions[0]) {
 512       if (p->match != (p-1)->match && p->match != (p+1)->match) {
 513         // move to front of opcode list to reduce miss penalty
 514         while (--p >= &instructions[0])
 515           *(p+1) = *p;
 516         instructions[0] = desc;
 517       }
 518     }
 519
 520     opcode_cache[idx] = desc;
 521     opcode_cache[idx].match = insn.bits();
 522   }
 523
 524   return xlen == 64 ? desc.rv64 : desc.rv32;
 525 }
 526
 527 void processor_t::register_insn(insn_desc_t desc)
 528 {
 529   instructions.push_back(desc);
 530 }
 531
 532 void processor_t::build_opcode_map()
 533 {
 534   struct cmp {
 535     bool operator()(const insn_desc_t& lhs, const insn_desc_t& rhs) {
 536       if (lhs.match == rhs.match)
 537         return lhs.mask > rhs.mask;
 538       return lhs.match > rhs.match;
 539     }
 540   };
 541   std::sort(instructions.begin(), instructions.end(), cmp());
 542
 543   for (size_t i = 0; i < OPCODE_CACHE_SIZE; i++)
 544     opcode_cache[i] = {1, 0, &illegal_instruction, &illegal_instruction};
 545 }
 546
 547 void processor_t::register_extension(extension_t* x)
 548 {
 549   for (auto insn : x->get_instructions())
 550     register_insn(insn);
 551   build_opcode_map();
 552   for (auto disasm_insn : x->get_disasms())
 553     disassembler->add_insn(disasm_insn);
 554   if (ext != NULL)
 555     throw std::logic_error("only one extension may be registered");
 556   ext = x;
 557   x->set_processor(this);
 558 }
 559
 560 void processor_t::register_base_instructions()
 561 {
 562   #define DECLARE_INSN(name, match, mask) \
 563     insn_bits_t name##_match = (match), name##_mask = (mask);
 564   #include "encoding.h"
 565   #undef DECLARE_INSN
 566
 567   #define DEFINE_INSN(name) \
 568     REGISTER_INSN(this, name, name##_match, name##_mask)
 569   #include "insn_list.h"
 570   #undef DEFINE_INSN
 571
 572   register_insn({0, 0, &illegal_instruction, &illegal_instruction});
 573   build_opcode_map();
 574 }
 575
 576 bool processor_t::load(reg_t addr, size_t len, uint8_t* bytes)
 577 {
 578   try {
 579     auto res = get_csr(addr / (max_xlen / 8));
 580     memcpy(bytes, &res, len);
 581     return true;
 582   } catch (trap_illegal_instruction& t) {
 583     return false;
 584   }
 585 }
 586
 587 bool processor_t::store(reg_t addr, size_t len, const uint8_t* bytes)
 588 {
 589   try {
 590     reg_t value = 0;
 591     memcpy(&value, bytes, len);
 592     set_csr(addr / (max_xlen / 8), value);
 593     return true;
 594   } catch (trap_illegal_instruction& t) {
 595     return false;
 596   }
 597 }