riscv/processor.cc

   1 // See LICENSE for license details.
   2
   3 #include "processor.h"
   4 #include "extension.h"
   5 #include "common.h"
   6 #include "config.h"
   7 #include "sim.h"
   8 #include "disasm.h"
   9 #include <cinttypes>
  10 #include <cmath>
  11 #include <cstdlib>
  12 #include <iostream>
  13 #include <assert.h>
  14 #include <limits.h>
  15 #include <stdexcept>
  16
  17 processor_t::processor_t(sim_t* _sim, mmu_t* _mmu, uint32_t _id)
  18   : sim(_sim), mmu(_mmu), ext(NULL), id(_id), opcode_bits(0)
  19 {
  20   reset(true);
  21   mmu->set_processor(this);
  22
  23   #define DECLARE_INSN(name, match, mask) REGISTER_INSN(this, name, match, mask)
  24   #include "opcodes.h"
  25   #undef DECLARE_INSN
  26 }
  27
  28 processor_t::~processor_t()
  29 {
  30 }
  31
  32 void state_t::reset()
  33 {
  34   // the ISA guarantees on boot that the PC is 0x2000 and the the processor
  35   // is in supervisor mode, and in 64-bit mode, if supported, with traps
  36   // and virtual memory disabled.
  37   sr = SR_S;
  38 #ifdef RISCV_ENABLE_64BIT
  39   sr |= SR_S64;
  40 #endif
  41   pc = 0x2000;
  42
  43   // the following state is undefined upon boot-up,
  44   // but we zero it for determinism
  45   XPR.reset();
  46   FPR.reset();
  47
  48   evec = 0;
  49   epc = 0;
  50   badvaddr = 0;
  51   cause = 0;
  52   pcr_k0 = 0;
  53   pcr_k1 = 0;
  54   count = 0;
  55   compare = 0;
  56   cycle = 0;
  57   fsr = 0;
  58
  59   load_reservation = -1;
  60 }
  61
  62 void processor_t::reset(bool value)
  63 {
  64   if (run == !value)
  65     return;
  66   run = !value;
  67
  68   state.reset(); // reset the core
  69   if (ext)
  70     ext->reset(); // reset the extension
  71 }
  72
  73 uint32_t processor_t::set_fsr(uint32_t val)
  74 {
  75   uint32_t old_fsr = state.fsr;
  76   state.fsr = val & ~FSR_ZERO; // clear FSR bits that read as zero
  77   return old_fsr;
  78 }
  79
  80 void processor_t::take_interrupt()
  81 {
  82   uint32_t interrupts = (state.sr & SR_IP) >> SR_IP_SHIFT;
  83   interrupts &= (state.sr & SR_IM) >> SR_IM_SHIFT;
  84
  85   if (interrupts && (state.sr & SR_EI))
  86     for (int i = 0; ; i++, interrupts >>= 1)
  87       if (interrupts & 1)
  88         throw trap_t((1ULL << ((state.sr & SR_S64) ? 63 : 31)) + i);
  89 }
  90
  91 void processor_t::step(size_t n, bool noisy)
  92 {
  93   if(!run)
  94     return;
  95
  96   size_t i = 0;
  97   reg_t npc = state.pc;
  98   mmu_t* _mmu = mmu;
  99
 100   try
 101   {
 102     take_interrupt();
 103
 104     // execute_insn fetches and executes one instruction
 105     #define execute_insn(noisy) \
 106       do { \
 107         mmu_t::insn_fetch_t fetch = _mmu->load_insn(npc); \
 108         if(noisy) disasm(fetch.insn.insn, npc); \
 109         npc = fetch.func(this, fetch.insn.insn, npc); \
 110       } while(0)
 111
 112
 113     // special execute_insn  for commit log dumping
 114 #ifdef RISCV_ENABLE_COMMITLOG
 115     //static disassembler disasmblr;
 116     #undef execute_insn
 117     #define execute_insn(noisy) \
 118       do { \
 119         mmu_t::insn_fetch_t fetch = _mmu->load_insn(npc); \
 120         if(noisy) disasm(fetch.insn.insn, npc); \
 121         bool in_spvr = state.sr & SR_S; \
 122         if (!in_spvr) fprintf(stderr, "\n0x%016" PRIx64 " (0x%08" PRIx32 ") ", npc, fetch.insn.insn.bits()); \
 123         /*if (!in_spvr) fprintf(stderr, "\n0x%016" PRIx64 " (0x%08" PRIx32 ") %s  ", npc, fetch.insn.insn.bits(), disasmblr.disassemble(fetch.insn.insn).c_str());*/ \
 124         npc = fetch.func(this, fetch.insn.insn, npc); \
 125       } while(0)
 126 #endif
 127
 128     if(noisy) for( ; i < n; i++) // print out instructions as we go
 129       execute_insn(true);
 130     else
 131     {
 132       // unrolled for speed
 133       for( ; n > 3 && i < n-3; i+=4)
 134       {
 135         execute_insn(false);
 136         execute_insn(false);
 137         execute_insn(false);
 138         execute_insn(false);
 139       }
 140       for( ; i < n; i++)
 141         execute_insn(false);
 142     }
 143
 144     state.pc = npc;
 145   }
 146   catch(trap_t& t)
 147   {
 148     take_trap(npc, t, noisy);
 149   }
 150
 151   state.cycle += i;
 152
 153   // update timer and possibly register a timer interrupt
 154   uint32_t old_count = state.count;
 155   state.count += i;
 156   if(old_count < state.compare && uint64_t(old_count) + i >= state.compare)
 157     set_interrupt(IRQ_TIMER, true);
 158 }
 159
 160 void processor_t::take_trap(reg_t pc, trap_t& t, bool noisy)
 161 {
 162   if (noisy)
 163     fprintf(stderr, "core %3d: exception %s, epc 0x%016" PRIx64 "\n",
 164             id, t.name(), pc);
 165
 166   // switch to supervisor, set previous supervisor bit, disable interrupts
 167   set_pcr(PCR_SR, (((state.sr & ~SR_EI) | SR_S) & ~SR_PS & ~SR_PEI) |
 168                   ((state.sr & SR_S) ? SR_PS : 0) |
 169                   ((state.sr & SR_EI) ? SR_PEI : 0));
 170
 171   yield_load_reservation();
 172   state.cause = t.cause();
 173   state.epc = pc;
 174   state.pc = state.evec;
 175
 176   t.side_effects(&state); // might set badvaddr etc.
 177 }
 178
 179 void processor_t::deliver_ipi()
 180 {
 181   if (run)
 182     set_pcr(PCR_CLR_IPI, 1);
 183 }
 184
 185 void processor_t::disasm(insn_t insn, reg_t pc)
 186 {
 187   // the disassembler is stateless, so we share it
 188   static disassembler disasm;
 189   fprintf(stderr, "core %3d: 0x%016" PRIx64 " (0x%08" PRIx32 ") %s\n",
 190           id, state.pc, insn.bits(), disasm.disassemble(insn).c_str());
 191 }
 192
 193 reg_t processor_t::set_pcr(int which, reg_t val)
 194 {
 195   reg_t old_pcr = get_pcr(which);
 196
 197   switch (which)
 198   {
 199     case PCR_SR:
 200       state.sr = (val & ~SR_IP) | (state.sr & SR_IP);
 201 #ifndef RISCV_ENABLE_64BIT
 202       state.sr &= ~(SR_S64 | SR_U64);
 203 #endif
 204 #ifndef RISCV_ENABLE_FPU
 205       state.sr &= ~SR_EF;
 206 #endif
 207 #ifndef RISCV_ENABLE_VEC
 208       state.sr &= ~SR_EV;
 209 #endif
 210       state.sr &= ~SR_ZERO;
 211       mmu->flush_tlb();
 212       break;
 213     case PCR_EPC:
 214       state.epc = val;
 215       break;
 216     case PCR_EVEC:
 217       state.evec = val;
 218       break;
 219     case PCR_COUNT:
 220       state.count = val;
 221       break;
 222     case PCR_COMPARE:
 223       set_interrupt(IRQ_TIMER, false);
 224       state.compare = val;
 225       break;
 226     case PCR_PTBR:
 227       state.ptbr = val & ~(PGSIZE-1);
 228       break;
 229     case PCR_SEND_IPI:
 230       sim->send_ipi(val);
 231       break;
 232     case PCR_CLR_IPI:
 233       set_interrupt(IRQ_IPI, val & 1);
 234       break;
 235     case PCR_SUP0:
 236       state.pcr_k0 = val;
 237       break;
 238     case PCR_SUP1:
 239       state.pcr_k1 = val;
 240       break;
 241     case PCR_TOHOST:
 242       if (state.tohost == 0)
 243         state.tohost = val;
 244       break;
 245     case PCR_FROMHOST:
 246       set_interrupt(IRQ_HOST, val != 0);
 247       state.fromhost = val;
 248       break;
 249   }
 250
 251   return old_pcr;
 252 }
 253
 254 reg_t processor_t::get_pcr(int which)
 255 {
 256   switch (which)
 257   {
 258     case PCR_SR:
 259       return state.sr;
 260     case PCR_EPC:
 261       return state.epc;
 262     case PCR_BADVADDR:
 263       return state.badvaddr;
 264     case PCR_EVEC:
 265       return state.evec;
 266     case PCR_COUNT:
 267       return state.count;
 268     case PCR_COMPARE:
 269       return state.compare;
 270     case PCR_CAUSE:
 271       return state.cause;
 272     case PCR_PTBR:
 273       return state.ptbr;
 274     case PCR_ASID:
 275       return 0;
 276     case PCR_FATC:
 277       mmu->flush_tlb();
 278       return 0;
 279     case PCR_HARTID:
 280       return id;
 281     case PCR_IMPL:
 282       return 1;
 283     case PCR_SUP0:
 284       return state.pcr_k0;
 285     case PCR_SUP1:
 286       return state.pcr_k1;
 287     case PCR_TOHOST:
 288       return state.tohost;
 289     case PCR_FROMHOST:
 290       return state.fromhost;
 291   }
 292   return -1;
 293 }
 294
 295 void processor_t::set_interrupt(int which, bool on)
 296 {
 297   uint32_t mask = (1 << (which + SR_IP_SHIFT)) & SR_IP;
 298   if (on)
 299     state.sr |= mask;
 300   else
 301     state.sr &= ~mask;
 302 }
 303
 304 reg_t illegal_instruction(processor_t* p, insn_t insn, reg_t pc)
 305 {
 306   throw trap_illegal_instruction();
 307 }
 308
 309 insn_func_t processor_t::decode_insn(insn_t insn)
 310 {
 311   bool rv64 = (state.sr & SR_S) ? (state.sr & SR_S64) : (state.sr & SR_U64);
 312
 313   auto key = insn.bits() & ((1L << opcode_bits)-1);
 314   for (auto it = opcode_map.find(key); it != opcode_map.end() && it->first == key; ++it)
 315     if ((insn.bits() & it->second.mask) == it->second.match)
 316       return rv64 ? it->second.rv64 : it->second.rv32;
 317
 318   return &illegal_instruction;
 319 }
 320
 321 void processor_t::register_insn(insn_desc_t desc)
 322 {
 323   assert(desc.mask & 1);
 324   if (opcode_bits == 0 || (desc.mask & ((1L << opcode_bits)-1)) != ((1L << opcode_bits)-1))
 325   {
 326     unsigned x = 0;
 327     while ((desc.mask & ((1L << (x+1))-1)) == ((1L << (x+1))-1) &&
 328            (opcode_bits == 0 || x <= opcode_bits))
 329       x++;
 330     opcode_bits = x;
 331
 332     decltype(opcode_map) new_map;
 333     for (auto it = opcode_map.begin(); it != opcode_map.end(); ++it)
 334       new_map.insert(std::make_pair(it->second.match & ((1L<<x)-1), it->second));
 335     opcode_map = new_map;
 336   }
 337
 338   opcode_map.insert(std::make_pair(desc.match & ((1L<<opcode_bits)-1), desc));
 339 }
 340
 341 void processor_t::register_extension(extension_t* x)
 342 {
 343   for (auto insn : x->get_instructions())
 344     register_insn(insn);
 345   if (ext != NULL)
 346     throw std::logic_error("only one extension may be registered");
 347   ext = x;
 348   x->set_processor(this);
 349 }