riscv/processor.cc

   1 // See LICENSE for license details.
   2
   3 #include "processor.h"
   4 #include "extension.h"
   5 #include "common.h"
   6 #include "config.h"
   7 #include "simif.h"
   8 #include "mmu.h"
   9 #include "disasm.h"
  10 #include <cinttypes>
  11 #include <cmath>
  12 #include <cstdlib>
  13 #include <iostream>
  14 #include <assert.h>
  15 #include <limits.h>
  16 #include <stdexcept>
  17 #include <algorithm>
  18
  19 #undef STATE
  20 #define STATE state
  21
  22 processor_t::processor_t(const char* isa, simif_t* sim, uint32_t id,
  23         bool halt_on_reset)
  24   : debug(false), halt_request(false), sim(sim), ext(NULL), id(id),
  25   halt_on_reset(halt_on_reset), last_pc(1), executions(1)
  26 {
  27   parse_isa_string(isa);
  28   register_base_instructions();
  29
  30   mmu = new mmu_t(sim, this);
  31
  32   disassembler = new disassembler_t(max_xlen);
  33   if (ext)
  34     for (auto disasm_insn : ext->get_disasms())
  35       disassembler->add_insn(disasm_insn);
  36
  37   reset();
  38 }
  39
  40 processor_t::~processor_t()
  41 {
  42 #ifdef RISCV_ENABLE_HISTOGRAM
  43   if (histogram_enabled)
  44   {
  45     fprintf(stderr, "PC Histogram size:%zu\n", pc_histogram.size());
  46     for (auto it : pc_histogram)
  47       fprintf(stderr, "%0" PRIx64 " %" PRIu64 "\n", it.first, it.second);
  48   }
  49 #endif
  50
  51   delete mmu;
  52   delete disassembler;
  53 }
  54
  55 static void bad_isa_string(const char* isa)
  56 {
  57   fprintf(stderr, "error: bad --isa option %s\n", isa);
  58   abort();
  59 }
  60
  61 void processor_t::parse_isa_string(const char* str)
  62 {
  63   std::string lowercase, tmp;
  64   for (const char *r = str; *r; r++)
  65     lowercase += std::tolower(*r);
  66
  67   const char* p = lowercase.c_str();
  68   const char* all_subsets = "imafdqc";
  69
  70   max_xlen = 64;
  71   state.misa = reg_t(2) << 62;
  72
  73   if (strncmp(p, "rv32", 4) == 0)
  74     max_xlen = 32, state.misa = reg_t(1) << 30, p += 4;
  75   else if (strncmp(p, "rv64", 4) == 0)
  76     p += 4;
  77   else if (strncmp(p, "rv", 2) == 0)
  78     p += 2;
  79
  80   if (!*p) {
  81     p = "imafdc";
  82   } else if (*p == 'g') { // treat "G" as "IMAFD"
  83     tmp = std::string("imafd") + (p+1);
  84     p = &tmp[0];
  85   } else if (*p != 'i') {
  86     bad_isa_string(str);
  87   }
  88
  89   isa_string = "rv" + std::to_string(max_xlen) + p;
  90   state.misa |= 1L << ('s' - 'a'); // advertise support for supervisor mode
  91   state.misa |= 1L << ('u' - 'a'); // advertise support for user mode
  92
  93   while (*p) {
  94     state.misa |= 1L << (*p - 'a');
  95
  96     if (auto next = strchr(all_subsets, *p)) {
  97       all_subsets = next + 1;
  98       p++;
  99     } else if (*p == 'x') {
 100       const char* ext = p+1, *end = ext;
 101       while (islower(*end))
 102         end++;
 103       register_extension(find_extension(std::string(ext, end - ext).c_str())());
 104       p = end;
 105     } else {
 106       bad_isa_string(str);
 107     }
 108   }
 109
 110   if (supports_extension('D') && !supports_extension('F'))
 111     bad_isa_string(str);
 112
 113   if (supports_extension('Q') && !supports_extension('D'))
 114     bad_isa_string(str);
 115
 116   if (supports_extension('Q') && max_xlen < 64)
 117     bad_isa_string(str);
 118
 119   max_isa = state.misa;
 120 }
 121
 122 void state_t::reset(reg_t max_isa)
 123 {
 124   memset(this, 0, sizeof(*this));
 125   misa = max_isa;
 126   prv = PRV_M;
 127   pc = DEFAULT_RSTVEC;
 128   tselect = 0;
 129   for (unsigned int i = 0; i < num_triggers; i++)
 130     mcontrol[i].type = 2;
 131 }
 132
 133 void processor_t::set_debug(bool value)
 134 {
 135   debug = value;
 136   if (ext)
 137     ext->set_debug(value);
 138 }
 139
 140 void processor_t::set_histogram(bool value)
 141 {
 142   histogram_enabled = value;
 143 #ifndef RISCV_ENABLE_HISTOGRAM
 144   if (value) {
 145     fprintf(stderr, "PC Histogram support has not been properly enabled;");
 146     fprintf(stderr, " please re-build the riscv-isa-run project using \"configure --enable-histogram\".\n");
 147   }
 148 #endif
 149 }
 150
 151 void processor_t::reset()
 152 {
 153   state.reset(max_isa);
 154   state.dcsr.halt = halt_on_reset;
 155   halt_on_reset = false;
 156   set_csr(CSR_MSTATUS, state.mstatus);
 157
 158   if (ext)
 159     ext->reset(); // reset the extension
 160
 161   if (sim)
 162     sim->proc_reset(id);
 163 }
 164
 165 // Count number of contiguous 0 bits starting from the LSB.
 166 static int ctz(reg_t val)
 167 {
 168   int res = 0;
 169   if (val)
 170     while ((val & 1) == 0)
 171       val >>= 1, res++;
 172   return res;
 173 }
 174
 175 void processor_t::take_interrupt(reg_t pending_interrupts)
 176 {
 177   reg_t mie = get_field(state.mstatus, MSTATUS_MIE);
 178   reg_t m_enabled = state.prv < PRV_M || (state.prv == PRV_M && mie);
 179   reg_t enabled_interrupts = pending_interrupts & ~state.mideleg & -m_enabled;
 180
 181   reg_t sie = get_field(state.mstatus, MSTATUS_SIE);
 182   reg_t s_enabled = state.prv < PRV_S || (state.prv == PRV_S && sie);
 183   // M-ints have highest priority; consider S-ints only if no M-ints pending
 184   if (enabled_interrupts == 0)
 185     enabled_interrupts = pending_interrupts & state.mideleg & -s_enabled;
 186
 187   if (state.dcsr.cause == 0 && enabled_interrupts) {
 188     // nonstandard interrupts have highest priority
 189     if (enabled_interrupts >> IRQ_M_EXT)
 190       enabled_interrupts = enabled_interrupts >> IRQ_M_EXT << IRQ_M_EXT;
 191     // external interrupts have next-highest priority
 192     else if (enabled_interrupts & (MIP_MEIP | MIP_SEIP))
 193       enabled_interrupts = enabled_interrupts & (MIP_MEIP | MIP_SEIP);
 194     // software interrupts have next-highest priority
 195     else if (enabled_interrupts & (MIP_MSIP | MIP_SSIP))
 196       enabled_interrupts = enabled_interrupts & (MIP_MSIP | MIP_SSIP);
 197     // timer interrupts have next-highest priority
 198     else if (enabled_interrupts & (MIP_MTIP | MIP_STIP))
 199       enabled_interrupts = enabled_interrupts & (MIP_MTIP | MIP_STIP);
 200     else
 201       abort();
 202
 203     throw trap_t(((reg_t)1 << (max_xlen-1)) | ctz(enabled_interrupts));
 204   }
 205 }
 206
 207 static int xlen_to_uxl(int xlen)
 208 {
 209   if (xlen == 32)
 210     return 1;
 211   if (xlen == 64)
 212     return 2;
 213   abort();
 214 }
 215
 216 reg_t processor_t::legalize_privilege(reg_t prv)
 217 {
 218   assert(prv <= PRV_M);
 219
 220   if (!supports_extension('U'))
 221     return PRV_M;
 222
 223   if (prv == PRV_H || !supports_extension('S'))
 224     return PRV_U;
 225
 226   return prv;
 227 }
 228
 229 void processor_t::set_privilege(reg_t prv)
 230 {
 231   mmu->flush_tlb();
 232   state.prv = legalize_privilege(prv);
 233 }
 234
 235 void processor_t::enter_debug_mode(uint8_t cause)
 236 {
 237   state.dcsr.cause = cause;
 238   state.dcsr.prv = state.prv;
 239   set_privilege(PRV_M);
 240   state.dpc = state.pc;
 241   state.pc = DEBUG_ROM_ENTRY;
 242 }
 243
 244 void processor_t::take_trap(trap_t& t, reg_t epc)
 245 {
 246   if (debug) {
 247     fprintf(stderr, "core %3d: exception %s, epc 0x%016" PRIx64 "\n",
 248             id, t.name(), epc);
 249     if (t.has_tval())
 250       fprintf(stderr, "core %3d:           tval 0x%016" PRIx64 "\n", id,
 251           t.get_tval());
 252   }
 253
 254   if (state.dcsr.cause) {
 255     if (t.cause() == CAUSE_BREAKPOINT) {
 256       state.pc = DEBUG_ROM_ENTRY;
 257     } else {
 258       state.pc = DEBUG_ROM_TVEC;
 259     }
 260     return;
 261   }
 262
 263   if (t.cause() == CAUSE_BREAKPOINT && (
 264               (state.prv == PRV_M && state.dcsr.ebreakm) ||
 265               (state.prv == PRV_S && state.dcsr.ebreaks) ||
 266               (state.prv == PRV_U && state.dcsr.ebreaku))) {
 267     enter_debug_mode(DCSR_CAUSE_SWBP);
 268     return;
 269   }
 270
 271   // by default, trap to M-mode, unless delegated to S-mode
 272   reg_t bit = t.cause();
 273   reg_t deleg = state.medeleg;
 274   bool interrupt = (bit & ((reg_t)1 << (max_xlen-1))) != 0;
 275   if (interrupt)
 276     deleg = state.mideleg, bit &= ~((reg_t)1 << (max_xlen-1));
 277   if (state.prv <= PRV_S && bit < max_xlen && ((deleg >> bit) & 1)) {
 278     // handle the trap in S-mode
 279     state.pc = state.stvec;
 280     state.scause = t.cause();
 281     state.sepc = epc;
 282     state.stval = t.get_tval();
 283
 284     reg_t s = state.mstatus;
 285     s = set_field(s, MSTATUS_SPIE, get_field(s, MSTATUS_SIE));
 286     s = set_field(s, MSTATUS_SPP, state.prv);
 287     s = set_field(s, MSTATUS_SIE, 0);
 288     set_csr(CSR_MSTATUS, s);
 289     set_privilege(PRV_S);
 290   } else {
 291     reg_t vector = (state.mtvec & 1) && interrupt ? 4*bit : 0;
 292     state.pc = (state.mtvec & ~(reg_t)1) + vector;
 293     state.mepc = epc;
 294     state.mcause = t.cause();
 295     state.mtval = t.get_tval();
 296
 297     reg_t s = state.mstatus;
 298     s = set_field(s, MSTATUS_MPIE, get_field(s, MSTATUS_MIE));
 299     s = set_field(s, MSTATUS_MPP, state.prv);
 300     s = set_field(s, MSTATUS_MIE, 0);
 301     set_csr(CSR_MSTATUS, s);
 302     set_privilege(PRV_M);
 303   }
 304 }
 305
 306 void processor_t::disasm(insn_t insn)
 307 {
 308   uint64_t bits = insn.bits() & ((1ULL << (8 * insn_length(insn.bits()))) - 1);
 309   if (last_pc != state.pc || last_bits != bits) {
 310     if (executions != 1) {
 311       fprintf(stderr, "core %3d: Executed %" PRIx64 " times\n", id, executions);
 312     }
 313
 314     fprintf(stderr, "core %3d: 0x%016" PRIx64 " (0x%08" PRIx64 ") %s\n",
 315             id, state.pc, bits, disassembler->disassemble(insn).c_str());
 316     last_pc = state.pc;
 317     last_bits = bits;
 318     executions = 1;
 319   } else {
 320     executions++;
 321   }
 322 }
 323
 324 int processor_t::paddr_bits()
 325 {
 326   assert(xlen == max_xlen);
 327   return max_xlen == 64 ? 50 : 34;
 328 }
 329
 330 void processor_t::set_csr(int which, reg_t val)
 331 {
 332   val = zext_xlen(val);
 333   reg_t delegable_ints = MIP_SSIP | MIP_STIP | MIP_SEIP
 334                        | ((ext != NULL) << IRQ_COP);
 335   reg_t all_ints = delegable_ints | MIP_MSIP | MIP_MTIP;
 336   switch (which)
 337   {
 338 #ifdef SPIKE_SIMPLEV
 339     case CSR_SVMVL:
 340       state.mvl = std::min(val, (uint64_t)63); // limited to XLEN width
 341       break;
 342     case CSR_SVREALVL:
 343       state.vl = std::min(val, state.mvl); // limited to MVL
 344       break;
 345     case CSR_SVVL:
 346       state.vl = std::min(state.mvl, state.XPR[val]);
 347       state.XPR.write(val, state.vl);
 348       break;
 349 #endif
 350     case CSR_FFLAGS:
 351       dirty_fp_state;
 352       state.fflags = val & (FSR_AEXC >> FSR_AEXC_SHIFT);
 353       break;
 354     case CSR_FRM:
 355       dirty_fp_state;
 356       state.frm = val & (FSR_RD >> FSR_RD_SHIFT);
 357       break;
 358     case CSR_FCSR:
 359       dirty_fp_state;
 360       state.fflags = (val & FSR_AEXC) >> FSR_AEXC_SHIFT;
 361       state.frm = (val & FSR_RD) >> FSR_RD_SHIFT;
 362       break;
 363     case CSR_MSTATUS: {
 364       if ((val ^ state.mstatus) &
 365           (MSTATUS_MPP | MSTATUS_MPRV | MSTATUS_SUM | MSTATUS_MXR))
 366         mmu->flush_tlb();
 367
 368       reg_t mask = MSTATUS_SIE | MSTATUS_SPIE | MSTATUS_MIE | MSTATUS_MPIE
 369                  | MSTATUS_FS | MSTATUS_MPRV | MSTATUS_SUM
 370                  | MSTATUS_MXR | MSTATUS_TW | MSTATUS_TVM
 371                  | MSTATUS_TSR | MSTATUS_UXL | MSTATUS_SXL |
 372                  (ext ? MSTATUS_XS : 0);
 373
 374       reg_t requested_mpp = legalize_privilege(get_field(val, MSTATUS_MPP));
 375       state.mstatus = set_field(state.mstatus, MSTATUS_MPP, requested_mpp);
 376       if (supports_extension('S'))
 377         mask |= MSTATUS_SPP;
 378
 379       state.mstatus = (state.mstatus & ~mask) | (val & mask);
 380
 381       bool dirty = (state.mstatus & MSTATUS_FS) == MSTATUS_FS;
 382       dirty |= (state.mstatus & MSTATUS_XS) == MSTATUS_XS;
 383       if (max_xlen == 32)
 384         state.mstatus = set_field(state.mstatus, MSTATUS32_SD, dirty);
 385       else
 386         state.mstatus = set_field(state.mstatus, MSTATUS64_SD, dirty);
 387
 388       state.mstatus = set_field(state.mstatus, MSTATUS_UXL, xlen_to_uxl(max_xlen));
 389       state.mstatus = set_field(state.mstatus, MSTATUS_UXL, xlen_to_uxl(max_xlen));
 390       state.mstatus = set_field(state.mstatus, MSTATUS_SXL, xlen_to_uxl(max_xlen));
 391       // U-XLEN == S-XLEN == M-XLEN
 392       xlen = max_xlen;
 393       break;
 394     }
 395     case CSR_MIP: {
 396       reg_t mask = MIP_SSIP | MIP_STIP;
 397       state.mip = (state.mip & ~mask) | (val & mask);
 398       break;
 399     }
 400     case CSR_MIE:
 401       state.mie = (state.mie & ~all_ints) | (val & all_ints);
 402       break;
 403     case CSR_MIDELEG:
 404       state.mideleg = (state.mideleg & ~delegable_ints) | (val & delegable_ints);
 405       break;
 406     case CSR_MEDELEG: {
 407       reg_t mask =
 408         (1 << CAUSE_MISALIGNED_FETCH) |
 409         (1 << CAUSE_BREAKPOINT) |
 410         (1 << CAUSE_USER_ECALL) |
 411         (1 << CAUSE_FETCH_PAGE_FAULT) |
 412         (1 << CAUSE_LOAD_PAGE_FAULT) |
 413         (1 << CAUSE_STORE_PAGE_FAULT);
 414       state.medeleg = (state.medeleg & ~mask) | (val & mask);
 415       break;
 416     }
 417     case CSR_MINSTRET:
 418     case CSR_MCYCLE:
 419       if (xlen == 32)
 420         state.minstret = (state.minstret >> 32 << 32) | (val & 0xffffffffU);
 421       else
 422         state.minstret = val;
 423       // The ISA mandates that if an instruction writes instret, the write
 424       // takes precedence over the increment to instret.  However, Spike
 425       // unconditionally increments instret after executing an instruction.
 426       // Correct for this artifact by decrementing instret here.
 427       state.minstret--;
 428       break;
 429     case CSR_MINSTRETH:
 430     case CSR_MCYCLEH:
 431       state.minstret = (val << 32) | (state.minstret << 32 >> 32);
 432       state.minstret--; // See comment above.
 433       break;
 434     case CSR_SCOUNTEREN:
 435       state.scounteren = val;
 436       break;
 437     case CSR_MCOUNTEREN:
 438       state.mcounteren = val;
 439       break;
 440     case CSR_SSTATUS: {
 441       reg_t mask = SSTATUS_SIE | SSTATUS_SPIE | SSTATUS_SPP | SSTATUS_FS
 442                  | SSTATUS_XS | SSTATUS_SUM | SSTATUS_MXR;
 443       return set_csr(CSR_MSTATUS, (state.mstatus & ~mask) | (val & mask));
 444     }
 445     case CSR_SIP: {
 446       reg_t mask = MIP_SSIP & state.mideleg;
 447       return set_csr(CSR_MIP, (state.mip & ~mask) | (val & mask));
 448     }
 449     case CSR_SIE:
 450       return set_csr(CSR_MIE,
 451                      (state.mie & ~state.mideleg) | (val & state.mideleg));
 452     case CSR_SATP: {
 453       mmu->flush_tlb();
 454       if (max_xlen == 32)
 455         state.satp = val & (SATP32_PPN | SATP32_MODE);
 456       if (max_xlen == 64 && (get_field(val, SATP64_MODE) == SATP_MODE_OFF ||
 457                              get_field(val, SATP64_MODE) == SATP_MODE_SV39 ||
 458                              get_field(val, SATP64_MODE) == SATP_MODE_SV48))
 459         state.satp = val & (SATP64_PPN | SATP64_MODE);
 460       break;
 461     }
 462     case CSR_SEPC: state.sepc = val & ~(reg_t)1; break;
 463     case CSR_STVEC: state.stvec = val >> 2 << 2; break;
 464     case CSR_SSCRATCH: state.sscratch = val; break;
 465     case CSR_SCAUSE: state.scause = val; break;
 466     case CSR_STVAL: state.stval = val; break;
 467     case CSR_MEPC: state.mepc = val & ~(reg_t)1; break;
 468     case CSR_MTVEC: state.mtvec = val & ~(reg_t)2; break;
 469     case CSR_MSCRATCH: state.mscratch = val; break;
 470     case CSR_MCAUSE: state.mcause = val; break;
 471     case CSR_MTVAL: state.mtval = val; break;
 472     case CSR_MISA: {
 473       // the write is ignored if increasing IALIGN would misalign the PC
 474       if (!(val & (1L << ('C' - 'A'))) && (state.pc & 2))
 475         break;
 476
 477       if (!(val & (1L << ('F' - 'A'))))
 478         val &= ~(1L << ('D' - 'A'));
 479
 480       // allow MAFDC bits in MISA to be modified
 481       reg_t mask = 0;
 482       mask |= 1L << ('M' - 'A');
 483       mask |= 1L << ('A' - 'A');
 484       mask |= 1L << ('F' - 'A');
 485       mask |= 1L << ('D' - 'A');
 486       mask |= 1L << ('C' - 'A');
 487       mask &= max_isa;
 488
 489       state.misa = (val & mask) | (state.misa & ~mask);
 490       break;
 491     }
 492     case CSR_TSELECT:
 493       if (val < state.num_triggers) {
 494         state.tselect = val;
 495       }
 496       break;
 497     case CSR_TDATA1:
 498       {
 499         mcontrol_t *mc = &state.mcontrol[state.tselect];
 500         if (mc->dmode && !state.dcsr.cause) {
 501           break;
 502         }
 503         mc->dmode = get_field(val, MCONTROL_DMODE(xlen));
 504         mc->select = get_field(val, MCONTROL_SELECT);
 505         mc->timing = get_field(val, MCONTROL_TIMING);
 506         mc->action = (mcontrol_action_t) get_field(val, MCONTROL_ACTION);
 507         mc->chain = get_field(val, MCONTROL_CHAIN);
 508         mc->match = (mcontrol_match_t) get_field(val, MCONTROL_MATCH);
 509         mc->m = get_field(val, MCONTROL_M);
 510         mc->h = get_field(val, MCONTROL_H);
 511         mc->s = get_field(val, MCONTROL_S);
 512         mc->u = get_field(val, MCONTROL_U);
 513         mc->execute = get_field(val, MCONTROL_EXECUTE);
 514         mc->store = get_field(val, MCONTROL_STORE);
 515         mc->load = get_field(val, MCONTROL_LOAD);
 516         // Assume we're here because of csrw.
 517         if (mc->execute)
 518           mc->timing = 0;
 519         trigger_updated();
 520       }
 521       break;
 522     case CSR_TDATA2:
 523       if (state.mcontrol[state.tselect].dmode && !state.dcsr.cause) {
 524         break;
 525       }
 526       if (state.tselect < state.num_triggers) {
 527         state.tdata2[state.tselect] = val;
 528       }
 529       break;
 530     case CSR_DCSR:
 531       state.dcsr.prv = get_field(val, DCSR_PRV);
 532       state.dcsr.step = get_field(val, DCSR_STEP);
 533       // TODO: ndreset and fullreset
 534       state.dcsr.ebreakm = get_field(val, DCSR_EBREAKM);
 535       state.dcsr.ebreakh = get_field(val, DCSR_EBREAKH);
 536       state.dcsr.ebreaks = get_field(val, DCSR_EBREAKS);
 537       state.dcsr.ebreaku = get_field(val, DCSR_EBREAKU);
 538       state.dcsr.halt = get_field(val, DCSR_HALT);
 539       break;
 540     case CSR_DPC:
 541       state.dpc = val & ~(reg_t)1;
 542       break;
 543     case CSR_DSCRATCH:
 544       state.dscratch = val;
 545       break;
 546   }
 547 }
 548
 549 reg_t processor_t::get_csr(int which)
 550 {
 551   uint32_t ctr_en = -1;
 552   if (state.prv < PRV_M)
 553     ctr_en &= state.mcounteren;
 554   if (state.prv < PRV_S)
 555     ctr_en &= state.scounteren;
 556   bool ctr_ok = (ctr_en >> (which & 31)) & 1;
 557
 558   if (ctr_ok) {
 559     if (which >= CSR_HPMCOUNTER3 && which <= CSR_HPMCOUNTER31)
 560       return 0;
 561     if (xlen == 32 && which >= CSR_HPMCOUNTER3H && which <= CSR_HPMCOUNTER31H)
 562       return 0;
 563   }
 564   if (which >= CSR_MHPMCOUNTER3 && which <= CSR_MHPMCOUNTER31)
 565     return 0;
 566   if (xlen == 32 && which >= CSR_MHPMCOUNTER3H && which <= CSR_MHPMCOUNTER31H)
 567     return 0;
 568   if (which >= CSR_MHPMEVENT3 && which <= CSR_MHPMEVENT31)
 569     return 0;
 570
 571   switch (which)
 572   {
 573 #ifdef SPIKE_SIMPLEV
 574     case CSR_SVVL:
 575     case CSR_SVREALVL:
 576       return state.vl;
 577     case CSR_SVMVL:
 578       return state.mvl;
 579 #endif
 580     case CSR_FFLAGS:
 581       require_fp;
 582       if (!supports_extension('F'))
 583         break;
 584       return state.fflags;
 585     case CSR_FRM:
 586       require_fp;
 587       if (!supports_extension('F'))
 588         break;
 589       return state.frm;
 590     case CSR_FCSR:
 591       require_fp;
 592       if (!supports_extension('F'))
 593         break;
 594       return (state.fflags << FSR_AEXC_SHIFT) | (state.frm << FSR_RD_SHIFT);
 595     case CSR_INSTRET:
 596     case CSR_CYCLE:
 597       if (ctr_ok)
 598         return state.minstret;
 599       break;
 600     case CSR_MINSTRET:
 601     case CSR_MCYCLE:
 602       return state.minstret;
 603     case CSR_INSTRETH:
 604     case CSR_CYCLEH:
 605       if (ctr_ok && xlen == 32)
 606         return state.minstret >> 32;
 607       break;
 608     case CSR_MINSTRETH:
 609     case CSR_MCYCLEH:
 610       if (xlen == 32)
 611         return state.minstret >> 32;
 612       break;
 613     case CSR_SCOUNTEREN: return state.scounteren;
 614     case CSR_MCOUNTEREN: return state.mcounteren;
 615     case CSR_SSTATUS: {
 616       reg_t mask = SSTATUS_SIE | SSTATUS_SPIE | SSTATUS_SPP | SSTATUS_FS
 617                  | SSTATUS_XS | SSTATUS_SUM | SSTATUS_MXR | SSTATUS_UXL;
 618       reg_t sstatus = state.mstatus & mask;
 619       if ((sstatus & SSTATUS_FS) == SSTATUS_FS ||
 620           (sstatus & SSTATUS_XS) == SSTATUS_XS)
 621         sstatus |= (xlen == 32 ? SSTATUS32_SD : SSTATUS64_SD);
 622       return sstatus;
 623     }
 624     case CSR_SIP: return state.mip & state.mideleg;
 625     case CSR_SIE: return state.mie & state.mideleg;
 626     case CSR_SEPC: return state.sepc & pc_alignment_mask();
 627     case CSR_STVAL: return state.stval;
 628     case CSR_STVEC: return state.stvec;
 629     case CSR_SCAUSE:
 630       if (max_xlen > xlen)
 631         return state.scause | ((state.scause >> (max_xlen-1)) << (xlen-1));
 632       return state.scause;
 633     case CSR_SATP:
 634       if (get_field(state.mstatus, MSTATUS_TVM))
 635         require_privilege(PRV_M);
 636       return state.satp;
 637     case CSR_SSCRATCH: return state.sscratch;
 638     case CSR_MSTATUS: return state.mstatus;
 639     case CSR_MIP: return state.mip;
 640     case CSR_MIE: return state.mie;
 641     case CSR_MEPC: return state.mepc & pc_alignment_mask();
 642     case CSR_MSCRATCH: return state.mscratch;
 643     case CSR_MCAUSE: return state.mcause;
 644     case CSR_MTVAL: return state.mtval;
 645     case CSR_MISA: return state.misa;
 646     case CSR_MARCHID: return 0;
 647     case CSR_MIMPID: return 0;
 648     case CSR_MVENDORID: return 0;
 649     case CSR_MHARTID: return id;
 650     case CSR_MTVEC: return state.mtvec;
 651     case CSR_MEDELEG: return state.medeleg;
 652     case CSR_MIDELEG: return state.mideleg;
 653     case CSR_TSELECT: return state.tselect;
 654     case CSR_TDATA1:
 655       if (state.tselect < state.num_triggers) {
 656         reg_t v = 0;
 657         mcontrol_t *mc = &state.mcontrol[state.tselect];
 658         v = set_field(v, MCONTROL_TYPE(xlen), mc->type);
 659         v = set_field(v, MCONTROL_DMODE(xlen), mc->dmode);
 660         v = set_field(v, MCONTROL_MASKMAX(xlen), mc->maskmax);
 661         v = set_field(v, MCONTROL_SELECT, mc->select);
 662         v = set_field(v, MCONTROL_TIMING, mc->timing);
 663         v = set_field(v, MCONTROL_ACTION, mc->action);
 664         v = set_field(v, MCONTROL_CHAIN, mc->chain);
 665         v = set_field(v, MCONTROL_MATCH, mc->match);
 666         v = set_field(v, MCONTROL_M, mc->m);
 667         v = set_field(v, MCONTROL_H, mc->h);
 668         v = set_field(v, MCONTROL_S, mc->s);
 669         v = set_field(v, MCONTROL_U, mc->u);
 670         v = set_field(v, MCONTROL_EXECUTE, mc->execute);
 671         v = set_field(v, MCONTROL_STORE, mc->store);
 672         v = set_field(v, MCONTROL_LOAD, mc->load);
 673         return v;
 674       } else {
 675         return 0;
 676       }
 677       break;
 678     case CSR_TDATA2:
 679       if (state.tselect < state.num_triggers) {
 680         return state.tdata2[state.tselect];
 681       } else {
 682         return 0;
 683       }
 684       break;
 685     case CSR_TDATA3: return 0;
 686     case CSR_DCSR:
 687       {
 688         uint32_t v = 0;
 689         v = set_field(v, DCSR_XDEBUGVER, 1);
 690         v = set_field(v, DCSR_EBREAKM, state.dcsr.ebreakm);
 691         v = set_field(v, DCSR_EBREAKH, state.dcsr.ebreakh);
 692         v = set_field(v, DCSR_EBREAKS, state.dcsr.ebreaks);
 693         v = set_field(v, DCSR_EBREAKU, state.dcsr.ebreaku);
 694         v = set_field(v, DCSR_STOPCYCLE, 0);
 695         v = set_field(v, DCSR_STOPTIME, 0);
 696         v = set_field(v, DCSR_CAUSE, state.dcsr.cause);
 697         v = set_field(v, DCSR_STEP, state.dcsr.step);
 698         v = set_field(v, DCSR_PRV, state.dcsr.prv);
 699         return v;
 700       }
 701     case CSR_DPC:
 702       return state.dpc & pc_alignment_mask();
 703     case CSR_DSCRATCH:
 704       return state.dscratch;
 705   }
 706   throw trap_illegal_instruction(0);
 707 }
 708
 709 reg_t illegal_instruction(processor_t* p, insn_t insn, reg_t pc)
 710 {
 711   throw trap_illegal_instruction(0);
 712 }
 713
 714 insn_func_t processor_t::decode_insn(insn_t insn)
 715 {
 716   // look up opcode in hash table
 717   size_t idx = insn.bits() % OPCODE_CACHE_SIZE;
 718   insn_desc_t desc = opcode_cache[idx];
 719
 720   if (unlikely(insn.bits() != desc.match)) {
 721     // fall back to linear search
 722     insn_desc_t* p = &instructions[0];
 723     while ((insn.bits() & p->mask) != p->match)
 724       p++;
 725     desc = *p;
 726
 727     if (p->mask != 0 && p > &instructions[0]) {
 728       if (p->match != (p-1)->match && p->match != (p+1)->match) {
 729         // move to front of opcode list to reduce miss penalty
 730         while (--p >= &instructions[0])
 731           *(p+1) = *p;
 732         instructions[0] = desc;
 733       }
 734     }
 735
 736     opcode_cache[idx] = desc;
 737     opcode_cache[idx].match = insn.bits();
 738   }
 739
 740   return xlen == 64 ? desc.rv64 : desc.rv32;
 741 }
 742
 743 void processor_t::register_insn(insn_desc_t desc)
 744 {
 745   instructions.push_back(desc);
 746 }
 747
 748 void processor_t::build_opcode_map()
 749 {
 750   struct cmp {
 751     bool operator()(const insn_desc_t& lhs, const insn_desc_t& rhs) {
 752       if (lhs.match == rhs.match)
 753         return lhs.mask > rhs.mask;
 754       return lhs.match > rhs.match;
 755     }
 756   };
 757   std::sort(instructions.begin(), instructions.end(), cmp());
 758
 759   for (size_t i = 0; i < OPCODE_CACHE_SIZE; i++)
 760     opcode_cache[i] = {0, 0, &illegal_instruction, &illegal_instruction};
 761 }
 762
 763 void processor_t::register_extension(extension_t* x)
 764 {
 765   for (auto insn : x->get_instructions())
 766     register_insn(insn);
 767   build_opcode_map();
 768   for (auto disasm_insn : x->get_disasms())
 769     disassembler->add_insn(disasm_insn);
 770   if (ext != NULL)
 771     throw std::logic_error("only one extension may be registered");
 772   ext = x;
 773   x->set_processor(this);
 774 }
 775
 776 void processor_t::register_base_instructions()
 777 {
 778   #define DECLARE_INSN(name, match, mask) \
 779     insn_bits_t name##_match = (match), name##_mask = (mask);
 780   #include "encoding.h"
 781   #undef DECLARE_INSN
 782
 783   #define DEFINE_INSN(name) \
 784     REGISTER_INSN(this, name, name##_match, name##_mask)
 785   #include "insn_list.h"
 786   #undef DEFINE_INSN
 787
 788   register_insn({0, 0, &illegal_instruction, &illegal_instruction});
 789   build_opcode_map();
 790 }
 791
 792 bool processor_t::load(reg_t addr, size_t len, uint8_t* bytes)
 793 {
 794   switch (addr)
 795   {
 796     case 0:
 797       if (len <= 4) {
 798         memset(bytes, 0, len);
 799         bytes[0] = get_field(state.mip, MIP_MSIP);
 800         return true;
 801       }
 802       break;
 803   }
 804
 805   return false;
 806 }
 807
 808 bool processor_t::store(reg_t addr, size_t len, const uint8_t* bytes)
 809 {
 810   switch (addr)
 811   {
 812     case 0:
 813       if (len <= 4) {
 814         state.mip = set_field(state.mip, MIP_MSIP, bytes[0]);
 815         return true;
 816       }
 817       break;
 818   }
 819
 820   return false;
 821 }
 822
 823 void processor_t::trigger_updated()
 824 {
 825   mmu->flush_tlb();
 826   mmu->check_triggers_fetch = false;
 827   mmu->check_triggers_load = false;
 828   mmu->check_triggers_store = false;
 829
 830   for (unsigned i = 0; i < state.num_triggers; i++) {
 831     if (state.mcontrol[i].execute) {
 832       mmu->check_triggers_fetch = true;
 833     }
 834     if (state.mcontrol[i].load) {
 835       mmu->check_triggers_load = true;
 836     }
 837     if (state.mcontrol[i].store) {
 838       mmu->check_triggers_store = true;
 839     }
 840   }
 841 }