riscv/processor.cc

   1 #include "processor.h"
   2 #include "common.h"
   3 #include "config.h"
   4 #include "sim.h"
   5 #include "disasm.h"
   6 #include <inttypes.h>
   7 #include <cmath>
   8 #include <cstdlib>
   9 #include <iostream>
  10 #include <assert.h>
  11
  12 processor_t::processor_t(sim_t* _sim, mmu_t* _mmu, uint32_t _id)
  13   : sim(*_sim), mmu(*_mmu), id(_id), utidx(0)
  14 {
  15   reset();
  16
  17   // create microthreads
  18   for (int i=0; i<MAX_UTS; i++)
  19     uts[i] = new processor_t(&sim, &mmu, id, i);
  20 }
  21
  22 processor_t::processor_t(sim_t* _sim, mmu_t* _mmu, uint32_t _id,
  23                          uint32_t _utidx)
  24   : sim(*_sim), mmu(*_mmu), id(_id)
  25 {
  26   reset();
  27   set_pcr(PCR_SR, sr | SR_EF | SR_EV);
  28   utidx = _utidx;
  29
  30   // microthreads don't possess their own microthreads
  31   for (int i=0; i<MAX_UTS; i++)
  32     uts[i] = NULL;
  33 }
  34
  35 processor_t::~processor_t()
  36 {
  37 }
  38
  39 void processor_t::reset()
  40 {
  41   run = false;
  42
  43   // the ISA guarantees on boot that the PC is 0x2000 and the the processor
  44   // is in supervisor mode, and in 64-bit mode, if supported, with traps
  45   // and virtual memory disabled.  we accomplish this by setting EVEC to
  46   // 0x2000 and *enabling* traps, then sending the core an IPI.
  47   set_pcr(PCR_SR, SR_S | SR_S64 | SR_ET | SR_IM);
  48   evec = 0x2000;
  49
  50   // the following state is undefined upon boot-up,
  51   // but we zero it for determinism
  52   XPR.reset();
  53   FPR.reset();
  54
  55   pc = 0;
  56   epc = 0;
  57   badvaddr = 0;
  58   cause = 0;
  59   pcr_k0 = 0;
  60   pcr_k1 = 0;
  61   count = 0;
  62   compare = 0;
  63   cycle = 0;
  64   set_fsr(0);
  65
  66   // vector stuff
  67   vecbanks = 0xff;
  68   vecbanks_count = 8;
  69   utidx = -1;
  70   vlmax = 32;
  71   vl = 0;
  72   nxfpr_bank = 256;
  73   nxpr_use = 32;
  74   nfpr_use = 32;
  75 }
  76
  77 void processor_t::set_fsr(uint32_t val)
  78 {
  79   fsr = val & ~FSR_ZERO; // clear FSR bits that read as zero
  80 }
  81
  82 void processor_t::vcfg()
  83 {
  84   if (nxpr_use + nfpr_use < 2)
  85     vlmax = nxfpr_bank * vecbanks_count;
  86   else
  87     vlmax = (nxfpr_bank / (nxpr_use + nfpr_use - 1)) * vecbanks_count;
  88
  89   vlmax = std::min(vlmax, MAX_UTS);
  90 }
  91
  92 void processor_t::setvl(int vlapp)
  93 {
  94   vl = std::min(vlmax, vlapp);
  95 }
  96
  97 void processor_t::take_interrupt()
  98 {
  99   uint32_t interrupts = interrupts_pending;
 100   interrupts &= (sr & SR_IM) >> SR_IM_SHIFT;
 101
 102   if(interrupts && (sr & SR_ET))
 103     for(int i = 0; ; i++, interrupts >>= 1)
 104       if(interrupts & 1)
 105         throw interrupt_t(i);
 106 }
 107
 108 void processor_t::step(size_t n, bool noisy)
 109 {
 110   if(!run)
 111     return;
 112
 113   size_t i = 0;
 114   while(1) try
 115   {
 116     take_interrupt();
 117
 118     mmu_t& _mmu = mmu;
 119     insn_t insn;
 120     insn_func_t func;
 121     reg_t npc = pc;
 122
 123     // execute_insn fetches and executes one instruction
 124     #define execute_insn(noisy) \
 125       do { \
 126         insn = _mmu.load_insn(npc, sr & SR_EC, &func); \
 127         if(noisy) disasm(insn,pc); \
 128         npc = func(this, insn, npc); \
 129         pc = npc; \
 130       } while(0)
 131
 132     if(noisy) for( ; i < n; i++) // print out instructions as we go
 133       execute_insn(true);
 134     else
 135     {
 136       // unrolled for speed
 137       for( ; n > 3 && i < n-3; i+=4)
 138       {
 139         execute_insn(false);
 140         execute_insn(false);
 141         execute_insn(false);
 142         execute_insn(false);
 143       }
 144       for( ; i < n; i++)
 145         execute_insn(false);
 146     }
 147
 148     break;
 149   }
 150   catch(trap_t t)
 151   {
 152     // an exception occurred in the target processor
 153     i++;
 154     take_trap(t,noisy);
 155   }
 156   catch(interrupt_t t)
 157   {
 158     i++;
 159     take_trap((1ULL << (8*sizeof(reg_t)-1)) + t.i, noisy);
 160   }
 161   catch(vt_command_t cmd)
 162   {
 163     // this microthread has finished
 164     i++;
 165     assert(cmd == vt_command_stop);
 166     break;
 167   }
 168   catch(halt_t t)
 169   {
 170     // sleep until IPI
 171     reset();
 172     return;
 173   }
 174
 175   cycle += i;
 176
 177   // update timer and possibly register a timer interrupt
 178   uint32_t old_count = count;
 179   count += i;
 180   if(old_count < compare && uint64_t(old_count) + i >= compare)
 181     interrupts_pending |= 1 << IRQ_TIMER;
 182 }
 183
 184 void processor_t::take_trap(reg_t t, bool noisy)
 185 {
 186   if(noisy)
 187   {
 188     if ((sreg_t)t < 0)
 189       printf("core %3d: interrupt %lld, pc 0x%016llx\n",
 190              id, (long long)(t << 1 >> 1), (unsigned long long)pc);
 191     else
 192       printf("core %3d: trap %s, pc 0x%016llx\n",
 193              id, trap_name(trap_t(t)), (unsigned long long)pc);
 194   }
 195
 196   // switch to supervisor, set previous supervisor bit, disable traps
 197   set_pcr(PCR_SR, (((sr & ~SR_ET) | SR_S) & ~SR_PS) | ((sr & SR_S) ? SR_PS : 0));
 198   cause = t;
 199   epc = pc;
 200   pc = evec;
 201   badvaddr = mmu.get_badvaddr();
 202 }
 203
 204 void processor_t::deliver_ipi()
 205 {
 206   set_pcr(PCR_CLR_IPI, 1);
 207   run = true;
 208 }
 209
 210 void processor_t::disasm(insn_t insn, reg_t pc)
 211 {
 212   // the disassembler is stateless, so we share it
 213   static disassembler disasm;
 214   printf("core %3d: 0x%016llx (0x%08x) %s\n", id, (unsigned long long)pc,
 215          insn.bits, disasm.disassemble(insn).c_str());
 216 }
 217
 218 void processor_t::set_pcr(int which, reg_t val)
 219 {
 220   switch (which)
 221   {
 222     case PCR_SR:
 223       sr = val & ~SR_ZERO; // clear SR bits that read as zero
 224 #ifndef RISCV_ENABLE_64BIT
 225       sr &= ~(SR_S64 | SR_U64);
 226 #endif
 227 #ifndef RISCV_ENABLE_FPU
 228       sr &= ~SR_EF;
 229 #endif
 230 #ifndef RISCV_ENABLE_RVC
 231       sr &= ~SR_EC;
 232 #endif
 233 #ifndef RISCV_ENABLE_VEC
 234       sr &= ~SR_EV;
 235 #endif
 236       // update MMU state and flush TLB
 237       mmu.set_vm_enabled(sr & SR_VM);
 238       mmu.set_supervisor(sr & SR_S);
 239       mmu.flush_tlb();
 240       // set the fixed-point register length
 241       xprlen = ((sr & SR_S) ? (sr & SR_S64) : (sr & SR_U64)) ? 64 : 32;
 242       break;
 243     case PCR_EPC:
 244       epc = val;
 245       break;
 246     case PCR_EVEC:
 247       evec = val;
 248       break;
 249     case PCR_COUNT:
 250       count = val;
 251       break;
 252     case PCR_COMPARE:
 253       interrupts_pending &= ~(1 << IRQ_TIMER);
 254       compare = val;
 255       break;
 256     case PCR_PTBR:
 257       mmu.set_ptbr(val);
 258       break;
 259     case PCR_SEND_IPI:
 260       sim.send_ipi(val);
 261       break;
 262     case PCR_CLR_IPI:
 263       if (val & 1)
 264         interrupts_pending |= (1 << IRQ_IPI);
 265       else
 266         interrupts_pending &= ~(1 << IRQ_IPI);
 267       break;
 268     case PCR_K0:
 269       pcr_k0 = val;
 270       break;
 271     case PCR_K1:
 272       pcr_k1 = val;
 273       break;
 274     case PCR_VECBANK:
 275       vecbanks = val & 0xff;
 276       vecbanks_count = __builtin_popcountll(vecbanks);
 277       break;
 278     case PCR_TOHOST:
 279       fromhost = 0;
 280       tohost = val;
 281       break;
 282     case PCR_FROMHOST:
 283       fromhost = val;
 284       tohost = 0;
 285       break;
 286   }
 287 }
 288
 289 reg_t processor_t::get_pcr(int which)
 290 {
 291   switch (which)
 292   {
 293     case PCR_SR:
 294       return sr;
 295     case PCR_EPC:
 296       return epc;
 297     case PCR_BADVADDR:
 298       return badvaddr;
 299     case PCR_EVEC:
 300       return evec;
 301     case PCR_COUNT:
 302       return count;
 303     case PCR_COMPARE:
 304       return compare;
 305     case PCR_CAUSE:
 306       return cause;
 307     case PCR_PTBR:
 308       return mmu.get_ptbr();
 309     case PCR_COREID:
 310       return id;
 311     case PCR_IMPL:
 312       return 1;
 313     case PCR_K0:
 314       return pcr_k0;
 315     case PCR_K1:
 316       return pcr_k1;
 317     case PCR_VECBANK:
 318       return vecbanks;
 319     case PCR_TOHOST:
 320       return tohost;
 321     case PCR_FROMHOST:
 322       return fromhost;
 323   }
 324   return -1;
 325 }