1 // See LICENSE for license details.
22 processor_t::processor_t(const char* isa
, sim_t
* sim
, uint32_t id
)
23 : sim(sim
), ext(NULL
), disassembler(new disassembler_t
),
24 id(id
), run(false), debug(false)
26 parse_isa_string(isa
);
28 mmu
= new mmu_t(sim
->mem
, sim
->memsz
);
29 mmu
->set_processor(this);
33 #define DECLARE_INSN(name, match, mask) REGISTER_INSN(this, name, match, mask)
39 processor_t::~processor_t()
41 #ifdef RISCV_ENABLE_HISTOGRAM
42 if (histogram_enabled
)
44 fprintf(stderr
, "PC Histogram size:%lu\n", pc_histogram
.size());
45 for(auto iterator
= pc_histogram
.begin(); iterator
!= pc_histogram
.end(); ++iterator
) {
46 fprintf(stderr
, "%0lx %lu\n", (iterator
->first
<< 2), iterator
->second
);
55 static void bad_isa_string(const char* isa
)
57 fprintf(stderr
, "error: bad --isa option %s\n", isa
);
61 void processor_t::parse_isa_string(const char* isa
)
64 const char* all_subsets
= "IMAFDC";
67 if (strncmp(p
, "RV32", 4) == 0)
68 max_xlen
= 32, p
+= 4;
69 else if (strncmp(p
, "RV64", 4) == 0)
71 else if (strncmp(p
, "RV", 2) == 0)
79 memset(subsets
, 0, sizeof(subsets
));
82 if (auto next
= strchr(all_subsets
, *p
)) {
83 subsets
[(int)*p
] = true;
84 all_subsets
= next
+ 1;
86 } else if (*p
== 'X') {
87 const char* ext
= p
+1, *end
= ext
;
90 register_extension(find_extension(std::string(ext
, end
- ext
).c_str())());
97 if (supports_extension('D') && !supports_extension('F'))
101 void state_t::reset()
103 memset(this, 0, sizeof(*this));
104 mstatus
= set_field(mstatus
, MSTATUS_PRV
, PRV_M
);
105 mstatus
= set_field(mstatus
, MSTATUS_PRV1
, PRV_S
);
106 mstatus
= set_field(mstatus
, MSTATUS_PRV2
, PRV_S
);
108 load_reservation
= -1;
111 void processor_t::set_debug(bool value
)
115 ext
->set_debug(value
);
118 void processor_t::set_histogram(bool value
)
120 histogram_enabled
= value
;
123 void processor_t::reset(bool value
)
130 set_csr(CSR_MSTATUS
, state
.mstatus
);
133 ext
->reset(); // reset the extension
136 void processor_t::raise_interrupt(reg_t which
)
138 throw trap_t(((reg_t
)1 << (max_xlen
-1)) | which
);
141 void processor_t::take_interrupt()
143 int priv
= get_field(state
.mstatus
, MSTATUS_PRV
);
144 int ie
= get_field(state
.mstatus
, MSTATUS_IE
);
146 if (priv
< PRV_M
|| (priv
== PRV_M
&& ie
)) {
147 if (get_field(state
.mstatus
, MSTATUS_MSIP
))
148 raise_interrupt(IRQ_IPI
);
150 if (state
.fromhost
!= 0)
151 raise_interrupt(IRQ_HOST
);
154 if (priv
< PRV_S
|| (priv
== PRV_S
&& ie
)) {
155 if (get_field(state
.mstatus
, MSTATUS_SSIP
))
156 raise_interrupt(IRQ_IPI
);
158 if (state
.stip
&& get_field(state
.mstatus
, MSTATUS_STIE
))
159 raise_interrupt(IRQ_TIMER
);
163 static void commit_log(state_t
* state
, reg_t pc
, insn_t insn
)
165 #ifdef RISCV_ENABLE_COMMITLOG
166 if (get_field(state
->mstatus
, MSTATUS_IE
)) {
167 uint64_t mask
= (insn
.length() == 8 ? uint64_t(0) : (uint64_t(1) << (insn
.length() * 8))) - 1;
168 if (state
->log_reg_write
.addr
) {
169 fprintf(stderr
, "0x%016" PRIx64
" (0x%08" PRIx64
") %c%2" PRIu64
" 0x%016" PRIx64
"\n",
172 state
->log_reg_write
.addr
& 1 ? 'f' : 'x',
173 state
->log_reg_write
.addr
>> 1,
174 state
->log_reg_write
.data
);
176 fprintf(stderr
, "0x%016" PRIx64
" (0x%08" PRIx64
")\n", pc
, insn
.bits() & mask
);
179 state
->log_reg_write
.addr
= 0;
183 inline void processor_t::update_histogram(size_t pc
)
185 #ifdef RISCV_ENABLE_HISTOGRAM
186 size_t idx
= pc
>> 2;
191 static reg_t
execute_insn(processor_t
* p
, reg_t pc
, insn_fetch_t fetch
)
193 reg_t npc
= fetch
.func(p
, fetch
.insn
, pc
);
194 commit_log(p
->get_state(), pc
, fetch
.insn
);
195 p
->update_histogram(pc
);
199 static void update_timer(state_t
* state
, size_t instret
)
201 uint64_t count0
= (uint64_t)(uint32_t)state
->scount
;
202 state
->scount
+= instret
;
203 uint64_t before
= count0
- state
->stimecmp
;
204 if (int64_t(before
^ (before
+ instret
)) < 0)
208 static size_t next_timer(state_t
* state
)
210 return state
->stimecmp
- (uint32_t)state
->scount
;
213 void processor_t::step(size_t n
)
219 if (unlikely(!run
|| !n
))
221 n
= std::min(n
, next_timer(&state
) | 1U);
223 #define maybe_serialize() \
224 if (unlikely(pc == PC_SERIALIZE)) { \
226 state.serialized = true; \
238 insn_fetch_t fetch
= mmu
->load_insn(pc
);
239 if (!state
.serialized
)
241 pc
= execute_insn(this, pc
, fetch
);
247 else while (instret
< n
)
249 size_t idx
= _mmu
->icache_index(pc
);
250 auto ic_entry
= _mmu
->access_icache(pc
);
252 #define ICACHE_ACCESS(idx) { \
253 insn_fetch_t fetch = ic_entry->data; \
255 pc = execute_insn(this, pc, fetch); \
256 if (idx == mmu_t::ICACHE_ENTRIES-1) break; \
257 if (unlikely(ic_entry->tag != pc)) break; \
273 state
.pc
= take_trap(t
, pc
);
276 update_timer(&state
, instret
);
279 void processor_t::push_privilege_stack()
281 reg_t s
= state
.mstatus
;
282 s
= set_field(s
, MSTATUS_PRV2
, get_field(state
.mstatus
, MSTATUS_PRV1
));
283 s
= set_field(s
, MSTATUS_IE2
, get_field(state
.mstatus
, MSTATUS_IE1
));
284 s
= set_field(s
, MSTATUS_PRV1
, get_field(state
.mstatus
, MSTATUS_PRV
));
285 s
= set_field(s
, MSTATUS_IE1
, get_field(state
.mstatus
, MSTATUS_IE
));
286 s
= set_field(s
, MSTATUS_PRV
, PRV_M
);
287 s
= set_field(s
, MSTATUS_MPRV
, PRV_M
);
288 s
= set_field(s
, MSTATUS_IE
, 0);
289 set_csr(CSR_MSTATUS
, s
);
292 void processor_t::pop_privilege_stack()
294 reg_t s
= state
.mstatus
;
295 s
= set_field(s
, MSTATUS_PRV
, get_field(state
.mstatus
, MSTATUS_PRV1
));
296 s
= set_field(s
, MSTATUS_IE
, get_field(state
.mstatus
, MSTATUS_IE1
));
297 s
= set_field(s
, MSTATUS_PRV1
, get_field(state
.mstatus
, MSTATUS_PRV2
));
298 s
= set_field(s
, MSTATUS_IE1
, get_field(state
.mstatus
, MSTATUS_IE2
));
299 s
= set_field(s
, MSTATUS_PRV2
, PRV_U
);
300 s
= set_field(s
, MSTATUS_IE2
, 1);
301 set_csr(CSR_MSTATUS
, s
);
304 reg_t
processor_t::take_trap(trap_t
& t
, reg_t epc
)
307 fprintf(stderr
, "core %3d: exception %s, epc 0x%016" PRIx64
"\n",
310 reg_t tvec
= 0x40 * get_field(state
.mstatus
, MSTATUS_PRV
);
311 push_privilege_stack();
312 yield_load_reservation();
313 state
.mcause
= t
.cause();
315 t
.side_effects(&state
); // might set badvaddr etc.
319 void processor_t::deliver_ipi()
321 state
.mstatus
|= MSTATUS_MSIP
;
324 void processor_t::disasm(insn_t insn
)
326 uint64_t bits
= insn
.bits() & ((1ULL << (8 * insn_length(insn
.bits()))) - 1);
327 fprintf(stderr
, "core %3d: 0x%016" PRIx64
" (0x%08" PRIx64
") %s\n",
328 id
, state
.pc
, bits
, disassembler
->disassemble(insn
).c_str());
331 static bool validate_priv(reg_t priv
)
333 return priv
== PRV_U
|| priv
== PRV_S
|| priv
== PRV_M
;
336 static bool validate_arch(int max_xlen
, reg_t arch
)
338 if (max_xlen
== 64 && arch
== UA_RV64
)
340 return arch
== UA_RV32
;
343 static bool validate_vm(int max_xlen
, reg_t vm
)
345 if (max_xlen
== 64 && vm
== VM_SV39
)
347 if (max_xlen
== 32 && vm
== VM_SV32
)
349 return vm
== VM_MBARE
;
352 void processor_t::set_csr(int which
, reg_t val
)
358 state
.fflags
= val
& (FSR_AEXC
>> FSR_AEXC_SHIFT
);
362 state
.frm
= val
& (FSR_RD
>> FSR_RD_SHIFT
);
366 state
.fflags
= (val
& FSR_AEXC
) >> FSR_AEXC_SHIFT
;
367 state
.frm
= (val
& FSR_RD
) >> FSR_RD_SHIFT
;
372 state
.scount
= val
; break;
376 state
.scount
= (val
<< 32) | (uint32_t)state
.scount
;
380 if ((val
^ state
.mstatus
) & (MSTATUS_VM
| MSTATUS_PRV
| MSTATUS_MPRV
))
383 reg_t mask
= MSTATUS_SSIP
| MSTATUS_MSIP
| MSTATUS_IE
| MSTATUS_IE1
384 | MSTATUS_IE2
| MSTATUS_IE3
| MSTATUS_STIE
| MSTATUS_FS
;
387 state
.mstatus
= (state
.mstatus
& ~mask
) | (val
& mask
);
389 if (validate_vm(max_xlen
, get_field(val
, MSTATUS_VM
)))
390 state
.mstatus
= (state
.mstatus
& ~MSTATUS_VM
) | (val
& MSTATUS_VM
);
391 if (validate_priv(get_field(val
, MSTATUS_MPRV
)))
392 state
.mstatus
= (state
.mstatus
& ~MSTATUS_MPRV
) | (val
& MSTATUS_MPRV
);
393 if (validate_priv(get_field(val
, MSTATUS_PRV
)))
394 state
.mstatus
= (state
.mstatus
& ~MSTATUS_PRV
) | (val
& MSTATUS_PRV
);
395 if (validate_priv(get_field(val
, MSTATUS_PRV1
)))
396 state
.mstatus
= (state
.mstatus
& ~MSTATUS_PRV1
) | (val
& MSTATUS_PRV1
);
397 if (validate_priv(get_field(val
, MSTATUS_PRV2
)))
398 state
.mstatus
= (state
.mstatus
& ~MSTATUS_PRV2
) | (val
& MSTATUS_PRV2
);
399 if (validate_priv(get_field(val
, MSTATUS_PRV3
)))
400 state
.mstatus
= (state
.mstatus
& ~MSTATUS_PRV3
) | (val
& MSTATUS_PRV3
);
402 bool dirty
= (state
.mstatus
& MSTATUS_FS
) == MSTATUS_FS
;
403 dirty
|= (state
.mstatus
& MSTATUS_XS
) == MSTATUS_XS
;
405 if (max_xlen
== 32) {
406 state
.mstatus
= set_field(state
.mstatus
, MSTATUS32_SD
, dirty
);
408 state
.mstatus
= set_field(state
.mstatus
, MSTATUS64_SD
, dirty
);
410 if (validate_arch(max_xlen
, get_field(val
, MSTATUS64_UA
)))
411 state
.mstatus
= (state
.mstatus
& ~MSTATUS64_UA
) | (val
& MSTATUS64_UA
);
412 if (validate_arch(max_xlen
, get_field(val
, MSTATUS64_SA
)))
413 state
.mstatus
= (state
.mstatus
& ~MSTATUS64_SA
) | (val
& MSTATUS64_SA
);
414 switch (get_field(state
.mstatus
, MSTATUS_PRV
)) {
415 case PRV_U
: if (get_field(state
.mstatus
, MSTATUS64_UA
)) xlen
= 64; break;
416 case PRV_S
: if (get_field(state
.mstatus
, MSTATUS64_SA
)) xlen
= 64; break;
417 case PRV_M
: xlen
= 64; break;
425 reg_t ms
= state
.mstatus
;
426 ms
= set_field(ms
, MSTATUS_SSIP
, get_field(val
, SSTATUS_SIP
));
427 ms
= set_field(ms
, MSTATUS_IE
, get_field(val
, SSTATUS_IE
));
428 ms
= set_field(ms
, MSTATUS_IE1
, get_field(val
, SSTATUS_PIE
));
429 ms
= set_field(ms
, MSTATUS_PRV1
, get_field(val
, SSTATUS_PS
));
430 ms
= set_field(ms
, MSTATUS64_UA
, get_field(val
, SSTATUS_UA
));
431 ms
= set_field(ms
, MSTATUS_STIE
, get_field(val
, SSTATUS_TIE
));
432 ms
= set_field(ms
, MSTATUS_FS
, get_field(val
, SSTATUS_FS
));
433 ms
= set_field(ms
, MSTATUS_XS
, get_field(val
, SSTATUS_XS
));
434 return set_csr(CSR_MSTATUS
, ms
);
436 case CSR_SEPC
: state
.sepc
= val
; break;
437 case CSR_STVEC
: state
.stvec
= val
& ~3; break;
440 state
.stimecmp
= val
;
442 case CSR_SPTBR
: state
.sptbr
= val
& ~(PGSIZE
-1); break;
443 case CSR_SSCRATCH
: state
.sscratch
= val
; break;
444 case CSR_MEPC
: state
.mepc
= val
; break;
445 case CSR_MSCRATCH
: state
.mscratch
= val
; break;
446 case CSR_MCAUSE
: state
.mcause
= val
; break;
447 case CSR_MBADADDR
: state
.mbadaddr
= val
; break;
448 case CSR_SEND_IPI
: sim
->send_ipi(val
); break;
450 if (state
.tohost
== 0)
453 case CSR_FROMHOST
: state
.fromhost
= val
; break;
457 reg_t
processor_t::get_csr(int which
)
463 if (!supports_extension('F'))
468 if (!supports_extension('F'))
473 if (!supports_extension('F'))
475 return (state
.fflags
<< FSR_AEXC_SHIFT
) | (state
.frm
<< FSR_RD_SHIFT
);
491 return state
.scount
>> 32;
495 ss
= set_field(ss
, SSTATUS_SIP
, get_field(state
.mstatus
, MSTATUS_SSIP
));
496 ss
= set_field(ss
, SSTATUS_IE
, get_field(state
.mstatus
, MSTATUS_IE
));
497 ss
= set_field(ss
, SSTATUS_PIE
, get_field(state
.mstatus
, MSTATUS_IE1
));
498 ss
= set_field(ss
, SSTATUS_PS
, get_field(state
.mstatus
, MSTATUS_PRV1
));
499 ss
= set_field(ss
, SSTATUS_UA
, get_field(state
.mstatus
, MSTATUS64_UA
));
500 ss
= set_field(ss
, SSTATUS_TIE
, get_field(state
.mstatus
, MSTATUS_STIE
));
501 ss
= set_field(ss
, SSTATUS_TIP
, state
.stip
);
502 ss
= set_field(ss
, SSTATUS_FS
, get_field(state
.mstatus
, MSTATUS_FS
));
503 ss
= set_field(ss
, SSTATUS_XS
, get_field(state
.mstatus
, MSTATUS_XS
));
504 if (get_field(state
.mstatus
, MSTATUS64_SD
))
505 ss
= set_field(ss
, (xlen
== 32 ? SSTATUS32_SD
: SSTATUS64_SD
), 1);
508 case CSR_SEPC
: return state
.sepc
;
509 case CSR_SBADADDR
: return state
.sbadaddr
;
510 case CSR_STVEC
: return state
.stvec
;
511 case CSR_STIMECMP
: return state
.stimecmp
;
514 return state
.scause
| ((state
.scause
>> (max_xlen
-1)) << (xlen
-1));
516 case CSR_SPTBR
: return state
.sptbr
;
517 case CSR_SASID
: return 0;
518 case CSR_SSCRATCH
: return state
.sscratch
;
519 case CSR_MSTATUS
: return state
.mstatus
;
520 case CSR_MEPC
: return state
.mepc
;
521 case CSR_MSCRATCH
: return state
.mscratch
;
522 case CSR_MCAUSE
: return state
.mcause
;
523 case CSR_MBADADDR
: return state
.mbadaddr
;
525 sim
->get_htif()->tick(); // not necessary, but faster
528 sim
->get_htif()->tick(); // not necessary, but faster
529 return state
.fromhost
;
530 case CSR_SEND_IPI
: return 0;
531 case CSR_HARTID
: return id
;
550 throw trap_illegal_instruction();
553 reg_t
illegal_instruction(processor_t
* p
, insn_t insn
, reg_t pc
)
555 throw trap_illegal_instruction();
558 insn_func_t
processor_t::decode_insn(insn_t insn
)
560 size_t mask
= opcode_map
.size()-1;
561 insn_desc_t
* desc
= opcode_map
[insn
.bits() & mask
];
563 while ((insn
.bits() & desc
->mask
) != desc
->match
)
566 return xlen
== 64 ? desc
->rv64
: desc
->rv32
;
569 void processor_t::register_insn(insn_desc_t desc
)
571 assert(desc
.mask
& 1);
572 instructions
.push_back(desc
);
575 void processor_t::build_opcode_map()
578 for (auto& inst
: instructions
)
579 while ((inst
.mask
& buckets
) != buckets
)
584 decltype(insn_desc_t::match
) mask
;
585 cmp(decltype(mask
) mask
) : mask(mask
) {}
586 bool operator()(const insn_desc_t
& lhs
, const insn_desc_t
& rhs
) {
587 if ((lhs
.match
& mask
) != (rhs
.match
& mask
))
588 return (lhs
.match
& mask
) < (rhs
.match
& mask
);
589 return lhs
.match
< rhs
.match
;
592 std::sort(instructions
.begin(), instructions
.end(), cmp(buckets
-1));
594 opcode_map
.resize(buckets
);
595 opcode_store
.resize(instructions
.size() + 1);
598 for (size_t b
= 0, i
= 0; b
< buckets
; b
++)
600 opcode_map
[b
] = &opcode_store
[j
];
601 while (i
< instructions
.size() && b
== (instructions
[i
].match
& (buckets
-1)))
602 opcode_store
[j
++] = instructions
[i
++];
605 assert(j
== opcode_store
.size()-1);
606 opcode_store
[j
].match
= opcode_store
[j
].mask
= 0;
607 opcode_store
[j
].rv32
= &illegal_instruction
;
608 opcode_store
[j
].rv64
= &illegal_instruction
;
611 void processor_t::register_extension(extension_t
* x
)
613 for (auto insn
: x
->get_instructions())
616 for (auto disasm_insn
: x
->get_disasms())
617 disassembler
->add_insn(disasm_insn
);
619 throw std::logic_error("only one extension may be registered");
621 x
->set_processor(this);