riscv/processor.cc

   1 // See LICENSE for license details.
   2
   3 #include "processor.h"
   4 #include "extension.h"
   5 #include "common.h"
   6 #include "config.h"
   7 #include "sim.h"
   8 #include "htif.h"
   9 #include "disasm.h"
  10 #include "icache.h"
  11 #include <cinttypes>
  12 #include <cmath>
  13 #include <cstdlib>
  14 #include <iostream>
  15 #include <assert.h>
  16 #include <limits.h>
  17 #include <stdexcept>
  18 #include <algorithm>
  19
  20 processor_t::processor_t(sim_t* _sim, mmu_t* _mmu, uint32_t _id)
  21   : sim(_sim), mmu(_mmu), ext(NULL), disassembler(new disassembler_t),
  22     id(_id), run(false), debug(false)
  23 {
  24   reset(true);
  25   mmu->set_processor(this);
  26
  27   #define DECLARE_INSN(name, match, mask) REGISTER_INSN(this, name, match, mask)
  28   #include "encoding.h"
  29   #undef DECLARE_INSN
  30   build_opcode_map();
  31 }
  32
  33 processor_t::~processor_t()
  34 {
  35 }
  36
  37 void state_t::reset()
  38 {
  39   // the ISA guarantees on boot that the PC is 0x2000 and the the processor
  40   // is in supervisor mode, and in 64-bit mode, if supported, with traps
  41   // and virtual memory disabled.
  42   sr = SR_S | SR_S64;
  43   pc = 0x2000;
  44
  45   // the following state is undefined upon boot-up,
  46   // but we zero it for determinism
  47   XPR.reset();
  48   FPR.reset();
  49
  50   epc = 0;
  51   badvaddr = 0;
  52   evec = 0;
  53   ptbr = 0;
  54   pcr_k0 = 0;
  55   pcr_k1 = 0;
  56   cause = 0;
  57   tohost = 0;
  58   fromhost = 0;
  59   count = 0;
  60   compare = 0;
  61   fflags = 0;
  62   frm = 0;
  63
  64   load_reservation = -1;
  65 }
  66
  67 void processor_t::set_debug(bool value)
  68 {
  69   debug = value;
  70   if (ext)
  71     ext->set_debug(value);
  72 }
  73
  74 void processor_t::reset(bool value)
  75 {
  76   if (run == !value)
  77     return;
  78   run = !value;
  79
  80   state.reset(); // reset the core
  81   set_pcr(CSR_STATUS, state.sr);
  82
  83   if (ext)
  84     ext->reset(); // reset the extension
  85 }
  86
  87 void processor_t::take_interrupt()
  88 {
  89   uint32_t interrupts = (state.sr & SR_IP) >> SR_IP_SHIFT;
  90   interrupts &= (state.sr & SR_IM) >> SR_IM_SHIFT;
  91
  92   if (interrupts && (state.sr & SR_EI))
  93     for (int i = 0; ; i++, interrupts >>= 1)
  94       if (interrupts & 1)
  95         throw trap_t((1ULL << ((state.sr & SR_S64) ? 63 : 31)) + i);
  96 }
  97
  98 void processor_t::step(size_t n)
  99 {
 100   if(!run)
 101     return;
 102
 103   mmu_t* _mmu = mmu;
 104   auto count32 = decltype(state.compare)(state.count);
 105   bool count_le_compare = count32 <= state.compare;
 106   n = std::min(n, size_t(state.compare - count32) | 1);
 107
 108   try
 109   {
 110     take_interrupt();
 111
 112     // execute_insn fetches and executes one instruction
 113     #define execute_insn(noisy) \
 114       do { \
 115         insn_fetch_t fetch = mmu->load_insn(state.pc); \
 116         if(noisy) disasm(fetch.insn.insn); \
 117         state.pc = fetch.func(this, fetch.insn.insn, state.pc); \
 118       } while(0)
 119
 120
 121     // special execute_insn  for commit log dumping
 122 #ifdef RISCV_ENABLE_COMMITLOG
 123     //static disassembler disasmblr;
 124     #undef execute_insn
 125     #define execute_insn(noisy) \
 126       do { \
 127         insn_fetch_t fetch = _mmu->load_insn(state.pc); \
 128         if(noisy) disasm(fetch.insn.insn); \
 129         bool in_spvr = state.sr & SR_S; \
 130         if (!in_spvr) fprintf(stderr, "\n0x%016" PRIx64 " (0x%08" PRIx32 ") ", state.pc, fetch.insn.insn.bits()); \
 131         /*if (!in_spvr) fprintf(stderr, "\n0x%016" PRIx64 " (0x%08" PRIx32 ") %s  ", state.pc, fetch.insn.insn.bits(), disasmblr.disassemble(fetch.insn.insn).c_str());*/ \
 132         state.pc = fetch.func(this, fetch.insn.insn, state.pc); \
 133       } while(0)
 134 #endif
 135
 136     if (debug) // print out instructions as we go
 137     {
 138       for (size_t i = 0; i < n; state.count++, i++)
 139         execute_insn(true);
 140     }
 141     else while (n > 0)
 142     {
 143       size_t idx = (state.pc / sizeof(insn_t)) % ICACHE_SIZE;
 144       auto ic_entry_init = &_mmu->icache[idx], ic_entry = ic_entry_init;
 145
 146       #define update_count() { \
 147         size_t i = ic_entry - ic_entry_init; \
 148         state.count += i; \
 149         if (i >= n) break; \
 150         n -= i; }
 151
 152       #define ICACHE_ACCESS(idx) { \
 153         insn_t insn = ic_entry->data.insn.insn; \
 154         insn_func_t func = ic_entry->data.func; \
 155         if (unlikely(ic_entry->tag != state.pc)) break; \
 156         ic_entry++; \
 157         state.pc = func(this, insn, state.pc); }
 158
 159       switch (idx) while (true)
 160       {
 161         ICACHE_SWITCH;
 162         update_count();
 163         ic_entry_init = ic_entry = &_mmu->icache[0];
 164       }
 165
 166       _mmu->access_icache(state.pc);
 167       update_count();
 168     }
 169   }
 170   catch(trap_t& t)
 171   {
 172     take_trap(t);
 173   }
 174
 175   bool count_ge_compare =
 176     uint64_t(n) + decltype(state.compare)(state.count) >= state.compare;
 177   if (count_le_compare && count_ge_compare)
 178     set_interrupt(IRQ_TIMER, true);
 179 }
 180
 181 void processor_t::take_trap(trap_t& t)
 182 {
 183   if (debug)
 184     fprintf(stderr, "core %3d: exception %s, epc 0x%016" PRIx64 "\n",
 185             id, t.name(), state.pc);
 186
 187   // switch to supervisor, set previous supervisor bit, disable interrupts
 188   set_pcr(CSR_STATUS, (((state.sr & ~SR_EI) | SR_S) & ~SR_PS & ~SR_PEI) |
 189                       ((state.sr & SR_S) ? SR_PS : 0) |
 190                       ((state.sr & SR_EI) ? SR_PEI : 0));
 191
 192   yield_load_reservation();
 193   state.cause = t.cause();
 194   state.epc = state.pc;
 195   state.pc = state.evec;
 196
 197   t.side_effects(&state); // might set badvaddr etc.
 198 }
 199
 200 void processor_t::deliver_ipi()
 201 {
 202   if (run)
 203     set_pcr(CSR_CLEAR_IPI, 1);
 204 }
 205
 206 void processor_t::disasm(insn_t insn)
 207 {
 208   // the disassembler is stateless, so we share it
 209   fprintf(stderr, "core %3d: 0x%016" PRIx64 " (0x%08" PRIx32 ") %s\n",
 210           id, state.pc, insn.bits(), disassembler->disassemble(insn).c_str());
 211 }
 212
 213 reg_t processor_t::set_pcr(int which, reg_t val)
 214 {
 215   reg_t old_pcr = get_pcr(which);
 216
 217   switch (which)
 218   {
 219     case CSR_FFLAGS:
 220       state.fflags = val & (FSR_AEXC >> FSR_AEXC_SHIFT);
 221       break;
 222     case CSR_FRM:
 223       state.frm = val & (FSR_RD >> FSR_RD_SHIFT);
 224       break;
 225     case CSR_FCSR:
 226       state.fflags = (val & FSR_AEXC) >> FSR_AEXC_SHIFT;
 227       state.frm = (val & FSR_RD) >> FSR_RD_SHIFT;
 228       break;
 229     case CSR_STATUS:
 230       state.sr = (val & ~SR_IP) | (state.sr & SR_IP);
 231 #ifndef RISCV_ENABLE_64BIT
 232       state.sr &= ~(SR_S64 | SR_U64);
 233 #endif
 234 #ifndef RISCV_ENABLE_FPU
 235       state.sr &= ~SR_EF;
 236 #endif
 237       if (!ext)
 238         state.sr &= ~SR_EA;
 239       state.sr &= ~SR_ZERO;
 240       rv64 = (state.sr & SR_S) ? (state.sr & SR_S64) : (state.sr & SR_U64);
 241       mmu->flush_tlb();
 242       break;
 243     case CSR_EPC:
 244       state.epc = val;
 245       break;
 246     case CSR_EVEC:
 247       state.evec = val;
 248       break;
 249     case CSR_CYCLE:
 250     case CSR_TIME:
 251     case CSR_INSTRET:
 252     case CSR_COUNT:
 253       state.count = val;
 254       break;
 255     case CSR_COMPARE:
 256       set_interrupt(IRQ_TIMER, false);
 257       state.compare = val;
 258       break;
 259     case CSR_PTBR:
 260       state.ptbr = val & ~(PGSIZE-1);
 261       break;
 262     case CSR_SEND_IPI:
 263       sim->send_ipi(val);
 264       break;
 265     case CSR_CLEAR_IPI:
 266       set_interrupt(IRQ_IPI, val & 1);
 267       break;
 268     case CSR_SUP0:
 269       state.pcr_k0 = val;
 270       break;
 271     case CSR_SUP1:
 272       state.pcr_k1 = val;
 273       break;
 274     case CSR_TOHOST:
 275       if (state.tohost == 0)
 276         state.tohost = val;
 277       break;
 278     case CSR_FROMHOST:
 279       set_fromhost(val);
 280       break;
 281   }
 282
 283   return old_pcr;
 284 }
 285
 286 void processor_t::set_fromhost(reg_t val)
 287 {
 288   set_interrupt(IRQ_HOST, val != 0);
 289   state.fromhost = val;
 290 }
 291
 292 reg_t processor_t::get_pcr(int which)
 293 {
 294   switch (which)
 295   {
 296     case CSR_FFLAGS:
 297       return state.fflags;
 298     case CSR_FRM:
 299       return state.frm;
 300     case CSR_FCSR:
 301       return (state.fflags << FSR_AEXC_SHIFT) | (state.frm << FSR_RD_SHIFT);
 302     case CSR_STATUS:
 303       return state.sr;
 304     case CSR_EPC:
 305       return state.epc;
 306     case CSR_BADVADDR:
 307       return state.badvaddr;
 308     case CSR_EVEC:
 309       return state.evec;
 310     case CSR_CYCLE:
 311     case CSR_TIME:
 312     case CSR_INSTRET:
 313     case CSR_COUNT:
 314       return state.count;
 315     case CSR_COMPARE:
 316       return state.compare;
 317     case CSR_CAUSE:
 318       return state.cause;
 319     case CSR_PTBR:
 320       return state.ptbr;
 321     case CSR_ASID:
 322       return 0;
 323     case CSR_FATC:
 324       mmu->flush_tlb();
 325       return 0;
 326     case CSR_HARTID:
 327       return id;
 328     case CSR_IMPL:
 329       return 1;
 330     case CSR_SUP0:
 331       return state.pcr_k0;
 332     case CSR_SUP1:
 333       return state.pcr_k1;
 334     case CSR_TOHOST:
 335       sim->get_htif()->tick(); // not necessary, but faster
 336       return state.tohost;
 337     case CSR_FROMHOST:
 338       sim->get_htif()->tick(); // not necessary, but faster
 339       return state.fromhost;
 340     default:
 341       return -1;
 342   }
 343 }
 344
 345 void processor_t::set_interrupt(int which, bool on)
 346 {
 347   uint32_t mask = (1 << (which + SR_IP_SHIFT)) & SR_IP;
 348   if (on)
 349     state.sr |= mask;
 350   else
 351     state.sr &= ~mask;
 352 }
 353
 354 reg_t illegal_instruction(processor_t* p, insn_t insn, reg_t pc)
 355 {
 356   throw trap_illegal_instruction();
 357 }
 358
 359 insn_func_t processor_t::decode_insn(insn_t insn)
 360 {
 361   size_t mask = opcode_map.size()-1;
 362   insn_desc_t* desc = opcode_map[insn.bits() & mask];
 363
 364   while ((insn.bits() & desc->mask) != desc->match)
 365     desc++;
 366
 367   return rv64 ? desc->rv64 : desc->rv32;
 368 }
 369
 370 void processor_t::register_insn(insn_desc_t desc)
 371 {
 372   assert(desc.mask & 1);
 373   instructions.push_back(desc);
 374 }
 375
 376 void processor_t::build_opcode_map()
 377 {
 378   size_t buckets = -1;
 379   for (auto& inst : instructions)
 380     while ((inst.mask & buckets) != buckets)
 381       buckets /= 2;
 382   buckets++;
 383
 384   struct cmp {
 385     decltype(insn_desc_t::match) mask;
 386     cmp(decltype(mask) mask) : mask(mask) {}
 387     bool operator()(const insn_desc_t& lhs, const insn_desc_t& rhs) {
 388       if ((lhs.match & mask) != (rhs.match & mask))
 389         return (lhs.match & mask) < (rhs.match & mask);
 390       return lhs.match < rhs.match;
 391     }
 392   };
 393   std::sort(instructions.begin(), instructions.end(), cmp(buckets-1));
 394
 395   opcode_map.resize(buckets);
 396   opcode_store.resize(instructions.size() + 1);
 397
 398   size_t j = 0;
 399   for (size_t b = 0, i = 0; b < buckets; b++)
 400   {
 401     opcode_map[b] = &opcode_store[j];
 402     while (i < instructions.size() && b == (instructions[i].match & (buckets-1)))
 403       opcode_store[j++] = instructions[i++];
 404   }
 405
 406   assert(j == opcode_store.size()-1);
 407   opcode_store[j].match = opcode_store[j].mask = 0;
 408   opcode_store[j].rv32 = &illegal_instruction;
 409   opcode_store[j].rv64 = &illegal_instruction;
 410 }
 411
 412 void processor_t::register_extension(extension_t* x)
 413 {
 414   for (auto insn : x->get_instructions())
 415     register_insn(insn);
 416   build_opcode_map();
 417   for (auto disasm_insn : x->get_disasms())
 418     disassembler->add_insn(disasm_insn);
 419   if (ext != NULL)
 420     throw std::logic_error("only one extension may be registered");
 421   ext = x;
 422   x->set_processor(this);
 423 }