riscv/processor.cc

   1 #include "processor.h"
   2 #include <bfd.h>
   3 #include <dis-asm.h>
   4 #include <cmath>
   5 #include <cstdlib>
   6 #include <iostream>
   7 #include "common.h"
   8 #include "config.h"
   9 #include "sim.h"
  10 #include "softfloat.h"
  11
  12 processor_t::processor_t(sim_t* _sim, char* _mem, size_t _memsz)
  13   : sim(_sim), mmu(_mem,_memsz)
  14 {
  15   memset(R,0,sizeof(R));
  16   memset(FR,0,sizeof(FR));
  17   pc = 0;
  18   evec = 0;
  19   epc = 0;
  20   badvaddr = 0;
  21   cause = 0;
  22   pcr_k0 = 0;
  23   pcr_k1 = 0;
  24   tohost = 0;
  25   fromhost = 0;
  26   count = 0;
  27   compare = 0;
  28   interrupts_pending = 0;
  29   set_sr(SR_S | (support_64bit ? SR_SX : 0));
  30   set_fsr(0);
  31
  32   memset(counters,0,sizeof(counters));
  33
  34   // a few assumptions about endianness, including freg_t union
  35   static_assert(BYTE_ORDER == LITTLE_ENDIAN);
  36   static_assert(sizeof(freg_t) == 8);
  37   static_assert(sizeof(reg_t) == 8);
  38
  39   static_assert(sizeof(insn_t) == 4);
  40   static_assert(sizeof(uint128_t) == 16 && sizeof(int128_t) == 16);
  41 }
  42
  43 void processor_t::init(uint32_t _id)
  44 {
  45   id = _id;
  46 }
  47
  48 void processor_t::set_sr(uint32_t val)
  49 {
  50   sr = val & ~SR_ZERO;
  51   if(!support_64bit)
  52     sr &= ~(SR_SX | SR_UX);
  53   if(!support_fp)
  54     sr &= ~SR_EF;
  55
  56   gprlen = ((sr & SR_S) ? (sr & SR_SX) : (sr & SR_UX)) ? 64 : 32;
  57 }
  58
  59 void processor_t::set_fsr(uint32_t val)
  60 {
  61   fsr = val & ~FSR_ZERO;
  62   softfloat_roundingMode = (fsr & FSR_RD) >> FSR_RD_SHIFT;
  63 }
  64
  65 void processor_t::step(size_t n, bool noisy)
  66 {
  67   size_t i = 0;
  68   while(1) try
  69   {
  70     for( ; i < n; i++)
  71     {
  72       uint32_t interrupts = interrupts_pending & ((sr & SR_IM) >> SR_IM_SHIFT);
  73       if((sr & SR_ET) && interrupts)
  74       {
  75         for(int i = 0; interrupts; i++, interrupts >>= 1)
  76           if(interrupts & 1)
  77             throw trap_t(16+i);
  78       }
  79
  80       insn_t insn = mmu.load_insn(pc);
  81
  82       reg_t npc = pc+sizeof(insn);
  83
  84       if(noisy)
  85         disasm(insn,pc);
  86
  87       #include "execute.h"
  88
  89       pc = npc;
  90       R[0] = 0;
  91
  92       if(count++ == compare)
  93         interrupts_pending |= 1 << TIMER_IRQ;
  94     }
  95     return;
  96   }
  97   catch(trap_t t)
  98   {
  99     i++;
 100     take_trap(t,noisy);
 101   }
 102 }
 103
 104 void processor_t::take_trap(trap_t t, bool noisy)
 105 {
 106   demand(t < NUM_TRAPS, "internal error: bad trap number %d", int(t));
 107   demand(sr & SR_ET, "error mode on core %d!\ntrap %s, pc 0x%016llx",
 108          id, trap_name(t), (unsigned long long)pc);
 109   if(noisy)
 110     printf("core %3d: trap %s, pc 0x%016llx\n",
 111            id, trap_name(t), (unsigned long long)pc);
 112
 113   set_sr((((sr & ~SR_ET) | SR_S) & ~SR_PS) | ((sr & SR_S) ? SR_PS : 0));
 114   cause = t;
 115   epc = pc;
 116   pc = evec;
 117   badvaddr = mmu.get_badvaddr();
 118 }
 119
 120 void processor_t::disasm(insn_t insn, reg_t pc)
 121 {
 122   printf("core %3d: 0x%016llx (0x%08x) ",id,(unsigned long long)pc,insn.bits);
 123
 124   #ifdef RISCV_HAVE_LIBOPCODES
 125   disassemble_info info;
 126   INIT_DISASSEMBLE_INFO(info, stdout, fprintf);
 127   info.flavour = bfd_target_unknown_flavour;
 128   info.arch = bfd_arch_mips;
 129   info.mach = 101; // XXX bfd_mach_mips_riscv requires modified bfd.h
 130   info.endian = BFD_ENDIAN_LITTLE;
 131   info.buffer = (bfd_byte*)&insn;
 132   info.buffer_length = sizeof(insn);
 133   info.buffer_vma = pc;
 134
 135   demand(print_insn_little_mips(pc, &info) == sizeof(insn), "disasm bug!");
 136   #else
 137   printf("unknown");
 138   #endif
 139   printf("\n");
 140 }