riscv/processor.cc

   1 #include "processor.h"
   2 #include <bfd.h>
   3 #include <dis-asm.h>
   4 #include <cmath>
   5 #include <cstdlib>
   6 #include <iostream>
   7 #include "common.h"
   8 #include "config.h"
   9 #include "sim.h"
  10 #include "icsim.h"
  11 #include "softfloat.h"
  12 #include "platform.h" // softfloat isNaNF32UI, etc.
  13 #include "internals.h" // ditto
  14
  15 processor_t::processor_t(sim_t* _sim, char* _mem, size_t _memsz)
  16   : sim(_sim), mmu(_mem,_memsz)
  17 {
  18   memset(XPR,0,sizeof(XPR));
  19   memset(FPR,0,sizeof(FPR));
  20   pc = 0;
  21   evec = 0;
  22   epc = 0;
  23   badvaddr = 0;
  24   cause = 0;
  25   pcr_k0 = 0;
  26   pcr_k1 = 0;
  27   tohost = 0;
  28   fromhost = 0;
  29   count = 0;
  30   compare = 0;
  31   set_sr(SR_S | SR_SX);  // SX ignored if 64b mode not supported
  32   set_fsr(0);
  33
  34   memset(counters,0,sizeof(counters));
  35
  36   // vector stuff
  37   vecbanks = 0xff;
  38   vecbanks_count = 8;
  39   utidx = -1;
  40   vlmax = 32;
  41   vl = 0;
  42   nxfpr_bank = 256;
  43   nxpr_use = 32;
  44   nfpr_use = 32;
  45   for (int i=0; i<MAX_UTS; i++)
  46     uts[i] = NULL;
  47
  48   // a few assumptions about endianness, including freg_t union
  49   static_assert(BYTE_ORDER == LITTLE_ENDIAN);
  50   static_assert(sizeof(freg_t) == 8);
  51   static_assert(sizeof(reg_t) == 8);
  52
  53   static_assert(sizeof(insn_t) == 4);
  54   static_assert(sizeof(uint128_t) == 16 && sizeof(int128_t) == 16);
  55
  56   icsim = NULL;
  57   dcsim = NULL;
  58   itlbsim = NULL;
  59   dtlbsim = NULL;
  60 }
  61
  62 processor_t::~processor_t()
  63 {
  64   if(icsim)
  65     icsim->print_stats();
  66   delete icsim;
  67
  68   if(itlbsim)
  69     itlbsim->print_stats();
  70   delete itlbsim;
  71
  72   if(dcsim)
  73     dcsim->print_stats();
  74   delete dcsim;
  75
  76   if(dtlbsim)
  77     dtlbsim->print_stats();
  78   delete dtlbsim;
  79 }
  80
  81 void processor_t::init(uint32_t _id, icsim_t* default_icache,
  82                        icsim_t* default_dcache)
  83 {
  84   id = _id;
  85
  86   for (int i=0; i<MAX_UTS; i++)
  87   {
  88     uts[i] = new processor_t(sim, mmu.mem, mmu.memsz);
  89     uts[i]->id = id;
  90     uts[i]->set_sr(uts[i]->sr | SR_EF);
  91     uts[i]->set_sr(uts[i]->sr | SR_EV);
  92     uts[i]->utidx = i;
  93   }
  94
  95   #ifdef RISCV_ENABLE_ICSIM
  96   icsim = new icsim_t(*default_icache);
  97   mmu.set_icsim(icsim);
  98   itlbsim = new icsim_t(1, 8, 4096, "ITLB");
  99   mmu.set_itlbsim(itlbsim);
 100   #endif
 101   #ifdef RISCV_ENABLE_ICSIM
 102   dcsim = new icsim_t(*default_dcache);
 103   mmu.set_dcsim(dcsim);
 104   dtlbsim = new icsim_t(1, 8, 4096, "DTLB");
 105   mmu.set_dtlbsim(dtlbsim);
 106   #endif
 107 }
 108
 109 void processor_t::set_sr(uint32_t val)
 110 {
 111   sr = val & ~SR_ZERO;
 112 #ifndef RISCV_ENABLE_64BIT
 113   sr &= ~(SR_SX | SR_UX);
 114 #endif
 115 #ifndef RISCV_ENABLE_FPU
 116   sr &= ~SR_EF;
 117 #endif
 118 #ifndef RISCV_ENABLE_RVC
 119   sr &= ~SR_EC;
 120 #endif
 121 #ifndef RISCV_ENABLE_VEC
 122   sr &= ~SR_EV;
 123 #endif
 124
 125   mmu.set_vm_enabled(sr & SR_VM);
 126   mmu.set_supervisor(sr & SR_S);
 127   mmu.flush_tlb();
 128
 129   xprlen = ((sr & SR_S) ? (sr & SR_SX) : (sr & SR_UX)) ? 64 : 32;
 130 }
 131
 132 void processor_t::set_fsr(uint32_t val)
 133 {
 134   fsr = val & ~FSR_ZERO;
 135 }
 136
 137 void processor_t::vcfg()
 138 {
 139   if (nxpr_use + nfpr_use < 2)
 140     vlmax = nxfpr_bank * vecbanks_count;
 141   else
 142     vlmax = (nxfpr_bank / (nxpr_use + nfpr_use - 1)) * vecbanks_count;
 143
 144   vlmax = std::min(vlmax, MAX_UTS);
 145 }
 146
 147 void processor_t::setvl(int vlapp)
 148 {
 149   vl = std::min(vlmax, vlapp);
 150 }
 151
 152 void processor_t::step(size_t n, bool noisy)
 153 {
 154   size_t i = 0;
 155   while(1) try
 156   {
 157     for( ; i < n; i++)
 158     {
 159       uint32_t interrupts = (cause & CAUSE_IP) >> CAUSE_IP_SHIFT;
 160       interrupts &= (sr & SR_IM) >> SR_IM_SHIFT;
 161       if(interrupts && (sr & SR_ET))
 162         take_trap(trap_interrupt,noisy);
 163
 164       insn_t insn = mmu.load_insn(pc, sr & SR_EC);
 165
 166       reg_t npc = pc + insn_length(insn);
 167
 168       if(noisy)
 169         disasm(insn,pc);
 170
 171       #include "execute.h"
 172
 173       pc = npc;
 174       XPR[0] = 0;
 175
 176       if(count++ == compare)
 177         cause |= 1 << (TIMER_IRQ+CAUSE_IP_SHIFT);
 178     }
 179     return;
 180   }
 181   catch(trap_t t)
 182   {
 183     i++;
 184     take_trap(t,noisy);
 185   }
 186   catch(vt_command_t cmd)
 187   {
 188     if (cmd == vt_command_stop)
 189       return;
 190   }
 191 }
 192
 193 void processor_t::take_trap(trap_t t, bool noisy)
 194 {
 195   demand(t < NUM_TRAPS, "internal error: bad trap number %d", int(t));
 196   demand(sr & SR_ET, "error mode on core %d!\ntrap %s, pc 0x%016llx",
 197          id, trap_name(t), (unsigned long long)pc);
 198   if(noisy)
 199     printf("core %3d: trap %s, pc 0x%016llx\n",
 200            id, trap_name(t), (unsigned long long)pc);
 201
 202   set_sr((((sr & ~SR_ET) | SR_S) & ~SR_PS) | ((sr & SR_S) ? SR_PS : 0));
 203   cause = (cause & ~CAUSE_EXCCODE) | (t << CAUSE_EXCCODE_SHIFT);
 204   epc = pc;
 205   pc = evec;
 206   badvaddr = mmu.get_badvaddr();
 207 }
 208
 209 void processor_t::disasm(insn_t insn, reg_t pc)
 210 {
 211   printf("core %3d: 0x%016llx (0x%08x) ",id,(unsigned long long)pc,insn.bits);
 212
 213   #ifdef RISCV_HAVE_LIBOPCODES
 214   disassemble_info info;
 215   INIT_DISASSEMBLE_INFO(info, stdout, fprintf);
 216   info.flavour = bfd_target_unknown_flavour;
 217   info.arch = bfd_arch_mips;
 218   info.mach = 101; // XXX bfd_mach_mips_riscv requires modified bfd.h
 219   info.endian = BFD_ENDIAN_LITTLE;
 220   info.buffer = (bfd_byte*)&insn;
 221   info.buffer_length = sizeof(insn);
 222   info.buffer_vma = pc;
 223
 224   int ret = print_insn_little_mips(pc, &info);
 225   demand(ret == (INSN_IS_RVC(insn.bits) ? 2 : 4), "disasm bug!");
 226   #else
 227   printf("unknown");
 228   #endif
 229   printf("\n");
 230 }