1 // See LICENSE for license details.
19 #include "sv_insn_redirect.h"
25 processor_t::processor_t(const char* isa
, simif_t
* sim
, uint32_t id
,
27 : debug(false), halt_request(false), sim(sim
), ext(NULL
), id(id
),
28 halt_on_reset(halt_on_reset
), last_pc(1), executions(1)
33 parse_isa_string(isa
);
34 register_base_instructions();
37 mmu
= new sv_mmu_t(sim
, this);
39 mmu
= new mmu_t(sim
, this);
42 disassembler
= new disassembler_t(max_xlen
);
44 for (auto disasm_insn
: ext
->get_disasms())
45 disassembler
->add_insn(disasm_insn
);
50 processor_t::~processor_t()
52 #ifdef RISCV_ENABLE_HISTOGRAM
53 if (histogram_enabled
)
55 fprintf(stderr
, "PC Histogram size:%zu\n", pc_histogram
.size());
56 for (auto it
: pc_histogram
)
57 fprintf(stderr
, "%0" PRIx64
" %" PRIu64
"\n", it
.first
, it
.second
);
65 static void bad_isa_string(const char* isa
)
67 fprintf(stderr
, "error: bad --isa option %s\n", isa
);
71 void processor_t::parse_isa_string(const char* str
)
73 std::string lowercase
, tmp
;
74 for (const char *r
= str
; *r
; r
++)
75 lowercase
+= std::tolower(*r
);
77 const char* p
= lowercase
.c_str();
78 const char* all_subsets
= "imafdqc";
81 state
.misa
= reg_t(2) << 62;
83 if (strncmp(p
, "rv32", 4) == 0)
84 max_xlen
= 32, state
.misa
= reg_t(1) << 30, p
+= 4;
85 else if (strncmp(p
, "rv64", 4) == 0)
87 else if (strncmp(p
, "rv", 2) == 0)
92 } else if (*p
== 'g') { // treat "G" as "IMAFD"
93 tmp
= std::string("imafd") + (p
+1);
95 } else if (*p
!= 'i') {
99 isa_string
= "rv" + std::to_string(max_xlen
) + p
;
100 state
.misa
|= 1L << ('s' - 'a'); // advertise support for supervisor mode
101 state
.misa
|= 1L << ('u' - 'a'); // advertise support for user mode
104 state
.misa
|= 1L << (*p
- 'a');
106 if (auto next
= strchr(all_subsets
, *p
)) {
107 all_subsets
= next
+ 1;
109 } else if (*p
== 'x') {
110 const char* ext
= p
+1, *end
= ext
;
111 while (islower(*end
))
113 register_extension(find_extension(std::string(ext
, end
- ext
).c_str())());
120 if (supports_extension('D') && !supports_extension('F'))
123 if (supports_extension('Q') && !supports_extension('D'))
126 if (supports_extension('Q') && max_xlen
< 64)
129 max_isa
= state
.misa
;
132 void state_t::reset(reg_t max_isa
)
134 memset(this, 0, sizeof(*this));
139 for (unsigned int i
= 0; i
< num_triggers
; i
++)
140 mcontrol
[i
].type
= 2;
143 void sv_shape_t::setup_map()
146 int lims
[3] = {xsz
, ysz
, zsz
};
147 int idxs
[3] = {0,0,0};
150 case SV_SHAPE_PERM_XYZ
: order
[0] = 0; order
[1] = 1; order
[2] = 2; break;
151 case SV_SHAPE_PERM_XZY
: order
[0] = 0; order
[1] = 2; order
[2] = 1; break;
152 case SV_SHAPE_PERM_YXZ
: order
[0] = 1; order
[1] = 0; order
[2] = 2; break;
153 case SV_SHAPE_PERM_YZX
: order
[0] = 1; order
[1] = 2; order
[2] = 0; break;
154 case SV_SHAPE_PERM_ZXY
: order
[0] = 2; order
[1] = 0; order
[2] = 1; break;
155 case SV_SHAPE_PERM_ZYX
: order
[0] = 2; order
[1] = 1; order
[2] = 0; break;
157 for (int i
= 0; i
< 128; i
++)
159 uint8_t new_idx
= idxs
[0] + idxs
[1] * xsz
+ idxs
[2] * xsz
* ysz
;
161 for (int j
= 0; j
< 3; j
++)
163 idxs
[order
[j
]] = idxs
[order
[j
]] + 1;
164 if (idxs
[order
[j
]] != lims
[order
[j
]]) {
172 int state_t::sv_csr_sz()
180 sv_csr_t
&state_t::sv()
189 sv_shape_t
* state_t::get_shape(reg_t reg
)
191 if (prv
== PRV_M
|| prv
== PRV_S
|| reg
== 0) {
194 for (int i
= 0; i
< 3; i
++) {
195 if (remap
[i
].regidx
== reg
) {
202 void processor_t::set_debug(bool value
)
206 ext
->set_debug(value
);
209 void processor_t::set_histogram(bool value
)
211 histogram_enabled
= value
;
212 #ifndef RISCV_ENABLE_HISTOGRAM
214 fprintf(stderr
, "PC Histogram support has not been properly enabled;");
215 fprintf(stderr
, " please re-build the riscv-isa-run project using \"configure --enable-histogram\".\n");
220 void processor_t::reset()
222 state
.reset(max_isa
);
223 state
.dcsr
.halt
= halt_on_reset
;
224 halt_on_reset
= false;
225 set_csr(CSR_MSTATUS
, state
.mstatus
);
228 ext
->reset(); // reset the extension
234 // Count number of contiguous 0 bits starting from the LSB.
235 static int ctz(reg_t val
)
239 while ((val
& 1) == 0)
244 void processor_t::take_interrupt(reg_t pending_interrupts
)
246 reg_t mie
= get_field(state
.mstatus
, MSTATUS_MIE
);
247 reg_t m_enabled
= state
.prv
< PRV_M
|| (state
.prv
== PRV_M
&& mie
);
248 reg_t enabled_interrupts
= pending_interrupts
& ~state
.mideleg
& -m_enabled
;
250 reg_t sie
= get_field(state
.mstatus
, MSTATUS_SIE
);
251 reg_t s_enabled
= state
.prv
< PRV_S
|| (state
.prv
== PRV_S
&& sie
);
252 // M-ints have highest priority; consider S-ints only if no M-ints pending
253 if (enabled_interrupts
== 0)
254 enabled_interrupts
= pending_interrupts
& state
.mideleg
& -s_enabled
;
256 if (state
.dcsr
.cause
== 0 && enabled_interrupts
) {
257 // nonstandard interrupts have highest priority
258 if (enabled_interrupts
>> IRQ_M_EXT
)
259 enabled_interrupts
= enabled_interrupts
>> IRQ_M_EXT
<< IRQ_M_EXT
;
260 // external interrupts have next-highest priority
261 else if (enabled_interrupts
& (MIP_MEIP
| MIP_SEIP
))
262 enabled_interrupts
= enabled_interrupts
& (MIP_MEIP
| MIP_SEIP
);
263 // software interrupts have next-highest priority
264 else if (enabled_interrupts
& (MIP_MSIP
| MIP_SSIP
))
265 enabled_interrupts
= enabled_interrupts
& (MIP_MSIP
| MIP_SSIP
);
266 // timer interrupts have next-highest priority
267 else if (enabled_interrupts
& (MIP_MTIP
| MIP_STIP
))
268 enabled_interrupts
= enabled_interrupts
& (MIP_MTIP
| MIP_STIP
);
272 throw trap_t(((reg_t
)1 << (max_xlen
-1)) | ctz(enabled_interrupts
));
276 static int xlen_to_uxl(int xlen
)
285 reg_t
processor_t::legalize_privilege(reg_t prv
)
287 assert(prv
<= PRV_M
);
289 if (!supports_extension('U'))
292 if (prv
== PRV_H
|| !supports_extension('S'))
298 void processor_t::set_privilege(reg_t prv
)
301 state
.prv
= legalize_privilege(prv
);
304 void processor_t::enter_debug_mode(uint8_t cause
)
306 state
.dcsr
.cause
= cause
;
307 state
.dcsr
.prv
= state
.prv
;
308 set_privilege(PRV_M
);
309 state
.dpc
= state
.pc
;
310 state
.pc
= DEBUG_ROM_ENTRY
;
313 void processor_t::take_trap(trap_t
& t
, reg_t epc
)
316 fprintf(stderr
, "core %3d: exception %s, epc 0x%016" PRIx64
"\n",
319 fprintf(stderr
, "core %3d: tval 0x%016" PRIx64
"\n", id
,
323 if (state
.dcsr
.cause
) {
324 if (t
.cause() == CAUSE_BREAKPOINT
) {
325 state
.pc
= DEBUG_ROM_ENTRY
;
327 state
.pc
= DEBUG_ROM_TVEC
;
332 if (t
.cause() == CAUSE_BREAKPOINT
&& (
333 (state
.prv
== PRV_M
&& state
.dcsr
.ebreakm
) ||
334 (state
.prv
== PRV_S
&& state
.dcsr
.ebreaks
) ||
335 (state
.prv
== PRV_U
&& state
.dcsr
.ebreaku
))) {
336 enter_debug_mode(DCSR_CAUSE_SWBP
);
340 // by default, trap to M-mode, unless delegated to S-mode
341 reg_t bit
= t
.cause();
342 reg_t deleg
= state
.medeleg
;
343 bool interrupt
= (bit
& ((reg_t
)1 << (max_xlen
-1))) != 0;
345 deleg
= state
.mideleg
, bit
&= ~((reg_t
)1 << (max_xlen
-1));
346 if (state
.prv
<= PRV_S
&& bit
< max_xlen
&& ((deleg
>> bit
) & 1)) {
347 // handle the trap in S-mode
348 state
.pc
= state
.stvec
;
349 state
.scause
= t
.cause();
351 state
.stval
= t
.get_tval();
353 reg_t s
= state
.mstatus
;
354 s
= set_field(s
, MSTATUS_SPIE
, get_field(s
, MSTATUS_SIE
));
355 s
= set_field(s
, MSTATUS_SPP
, state
.prv
);
356 s
= set_field(s
, MSTATUS_SIE
, 0);
357 set_csr(CSR_MSTATUS
, s
);
358 set_privilege(PRV_S
);
360 reg_t vector
= (state
.mtvec
& 1) && interrupt
? 4*bit
: 0;
361 state
.pc
= (state
.mtvec
& ~(reg_t
)1) + vector
;
363 state
.mcause
= t
.cause();
364 state
.mtval
= t
.get_tval();
366 reg_t s
= state
.mstatus
;
367 s
= set_field(s
, MSTATUS_MPIE
, get_field(s
, MSTATUS_MIE
));
368 s
= set_field(s
, MSTATUS_MPP
, state
.prv
);
369 s
= set_field(s
, MSTATUS_MIE
, 0);
370 set_csr(CSR_MSTATUS
, s
);
371 set_privilege(PRV_M
);
375 void processor_t::disasm(insn_t insn
)
377 uint64_t bits
= insn
.bits() & ((1ULL << (8 * insn_length(insn
.bits()))) - 1);
378 if (last_pc
!= state
.pc
|| last_bits
!= bits
) {
379 if (executions
!= 1) {
380 fprintf(stderr
, "core %3d: Executed %" PRIx64
" times\n", id
, executions
);
383 fprintf(stderr
, "core %3d: 0x%016" PRIx64
" (0x%08" PRIx64
") %s\n",
384 id
, state
.pc
, bits
, disassembler
->disassemble(insn
).c_str());
393 int processor_t::paddr_bits()
395 assert(xlen
== max_xlen
);
396 return max_xlen
== 64 ? 50 : 34;
399 void processor_t::set_csr(int which
, reg_t val
)
401 val
= _zext_xlen(val
);
402 reg_t delegable_ints
= MIP_SSIP
| MIP_STIP
| MIP_SEIP
403 | ((ext
!= NULL
) << IRQ_COP
);
404 reg_t all_ints
= delegable_ints
| MIP_MSIP
| MIP_MTIP
;
405 fprintf(stderr
, "set CSR %x %lx\n", which
, val
);
410 state
.sv().mvl
= std::min(val
, (uint64_t)64); // limited to XLEN width
411 // TODO XXX throw exception if val == 0
412 fprintf(stderr
, "set MVL %lx\n", state
.sv().mvl
);
415 // bits 0-5: mvl - 6-11: vl - 12-17: srcoffs - 18-23: destoffs
416 set_csr(CSR_USVMVL
, get_field(val
, 0x1f )+1);
417 set_csr(CSR_USVVL
, get_field(val
, 0x1f<<6)+1);
418 state
.sv().srcoffs
= std::min(get_field(val
, 0x1f<<12), state
.sv().vl
-1);
419 state
.sv().destoffs
= std::min(get_field(val
, 0x1f<<18), state
.sv().vl
-1);
422 state
.sv().vl
= std::min(state
.sv().mvl
, val
);
423 // TODO XXX throw exception if val == 0
424 fprintf(stderr
, "set VL %lx\n", state
.sv().vl
);
435 uint64_t v
= (uint64_t)val
;
436 // identify which (pair) of SV config CAM registers are being set
437 int tbidx
= (which
- CSR_SVREGCFG0
) * 2;
438 fprintf(stderr
, "set REGCFG %d %lx\n", tbidx
, v
);
439 // lower 16 bits go into even, upper into odd...
440 state
.sv().sv_csrs
[tbidx
].u
= get_field(v
, 0xffffUL
);
441 state
.sv().sv_csrs
[tbidx
+1].u
= get_field(v
, 0xffffUL
<<16);
445 state
.sv().sv_csrs
[tbidx
+2].u
= get_field(v
, 0xffffUL
<<32);
446 state
.sv().sv_csrs
[tbidx
+3].u
= get_field(v
, 0xffffUL
<<48);
449 // clear out all CSRs above the one(s) being set: this ensures that
450 // when it comes to context-switching, it's clear what needs to be saved
451 for (int i
= tbidx
+clroffset
; i
< 16; i
++)
453 fprintf(stderr
, "clr REGCFG %d\n", i
);
454 state
.sv().sv_csrs
[i
].u
= 0;
456 // okaaay and now "unpack" the CAM to make it easier to use. this
457 // approach is not designed to be efficient right now. optimise later
458 // first clear the old tables
459 memset(state
.sv().sv_int_tb
, 0, sizeof(state
.sv().sv_int_tb
));
460 memset(state
.sv().sv_fp_tb
, 0, sizeof(state
.sv().sv_fp_tb
));
461 // now walk the CAM and unpack it
462 for (int i
= 0; i
< state
.sv_csr_sz(); i
++)
464 union sv_reg_csr_entry
*c
= &state
.sv().sv_csrs
[i
];
465 uint64_t idx
= c
->b
.regkey
;
471 // XXX damn. this basically duplicates sv_insn_t::get_regentry.
474 r
= &state
.sv().sv_int_tb
[idx
];
478 r
= &state
.sv().sv_fp_tb
[idx
];
480 r
->elwidth
= c
->b
.elwidth
;
481 r
->regidx
= c
->b
.regidx
;
482 r
->isvec
= c
->b
.isvec
;
484 fprintf(stderr
, "setting REGCFG type:%d isvec:%d %d %d\n",
485 c
->b
.type
, r
->isvec
, (int)idx
, (int)r
->regidx
);
498 // comments removed as it's near-identical to the regs version
500 uint64_t v
= (uint64_t)val
;
501 int tbidx
= (which
- CSR_SVPREDCFG0
) * 2;
502 fprintf(stderr
, "set PREDCFG %d %lx\n", tbidx
, v
);
503 state
.sv().sv_pred_csrs
[tbidx
].u
= get_field(v
, 0xffff);
504 state
.sv().sv_pred_csrs
[tbidx
+1].u
= get_field(v
, 0xffff0000);
508 state
.sv().sv_pred_csrs
[tbidx
+2].u
= get_field(v
, 0xffffUL
<<32);
509 state
.sv().sv_pred_csrs
[tbidx
+3].u
= get_field(v
, 0xffffUL
<<48);
512 for (int i
= tbidx
+clroffset
; i
< 16; i
++)
514 state
.sv().sv_pred_csrs
[i
].u
= 0;
516 memset(state
.sv().sv_pred_int_tb
, 0, sizeof(state
.sv().sv_pred_int_tb
));
517 memset(state
.sv().sv_pred_fp_tb
, 0, sizeof(state
.sv().sv_pred_fp_tb
));
518 for (int i
= 0; i
< state
.sv_csr_sz(); i
++)
520 union sv_pred_csr_entry
*c
= &state
.sv().sv_pred_csrs
[i
];
521 uint64_t idx
= c
->b
.regkey
;
527 // XXX damn. this basically duplicates sv_insn_t::get_predentry.
530 r
= &state
.sv().sv_pred_int_tb
[idx
];
534 r
= &state
.sv().sv_pred_fp_tb
[idx
];
536 r
->regidx
= c
->b
.regidx
;
539 r
->packed
= c
->b
.packed
;
541 fprintf(stderr
, "setting PREDCFG %d type:%d zero:%d %d %d\n",
542 i
, c
->b
.type
, r
->zero
, (int)idx
, (int)r
->regidx
);
548 state
.remap
[0].regidx
= get_field(val
, SV_REMAP_REGIDX0
);
549 state
.remap
[1].regidx
= get_field(val
, SV_REMAP_REGIDX1
);
550 state
.remap
[2].regidx
= get_field(val
, SV_REMAP_REGIDX2
);
551 state
.remap
[0].shape
= get_field(val
, SV_REMAP_SHAPE0
);
552 state
.remap
[1].shape
= get_field(val
, SV_REMAP_SHAPE1
);
553 state
.remap
[2].shape
= get_field(val
, SV_REMAP_SHAPE2
);
560 int shapeidx
= which
- CSR_USHAPE0
;
561 state
.shape
[shapeidx
].xsz
= get_field(val
, SV_SHAPE_XDIM
);
562 state
.shape
[shapeidx
].ysz
= get_field(val
, SV_SHAPE_YDIM
);
563 state
.shape
[shapeidx
].zsz
= get_field(val
, SV_SHAPE_ZDIM
);
564 state
.shape
[shapeidx
].offs
= (get_field(val
, (1<<7 )) ? 0x1 : 0) |
565 (get_field(val
, (1<<15)) ? 0x2 : 0) |
566 (get_field(val
, (1<<23)) ? 0x4 : 0);
567 state
.shape
[shapeidx
].permute
= get_field(val
, SV_SHAPE_PERM
);
568 state
.shape
[shapeidx
].setup_map();
574 state
.fflags
= val
& (FSR_AEXC
>> FSR_AEXC_SHIFT
);
578 state
.frm
= val
& (FSR_RD
>> FSR_RD_SHIFT
);
582 state
.fflags
= (val
& FSR_AEXC
) >> FSR_AEXC_SHIFT
;
583 state
.frm
= (val
& FSR_RD
) >> FSR_RD_SHIFT
;
586 if ((val
^ state
.mstatus
) &
587 (MSTATUS_MPP
| MSTATUS_MPRV
| MSTATUS_SUM
| MSTATUS_MXR
))
590 reg_t mask
= MSTATUS_SIE
| MSTATUS_SPIE
| MSTATUS_MIE
| MSTATUS_MPIE
591 | MSTATUS_FS
| MSTATUS_MPRV
| MSTATUS_SUM
592 | MSTATUS_MXR
| MSTATUS_TW
| MSTATUS_TVM
593 | MSTATUS_TSR
| MSTATUS_UXL
| MSTATUS_SXL
|
594 (ext
? MSTATUS_XS
: 0);
596 reg_t requested_mpp
= legalize_privilege(get_field(val
, MSTATUS_MPP
));
597 state
.mstatus
= set_field(state
.mstatus
, MSTATUS_MPP
, requested_mpp
);
598 if (supports_extension('S'))
601 state
.mstatus
= (state
.mstatus
& ~mask
) | (val
& mask
);
603 bool dirty
= (state
.mstatus
& MSTATUS_FS
) == MSTATUS_FS
;
604 dirty
|= (state
.mstatus
& MSTATUS_XS
) == MSTATUS_XS
;
606 state
.mstatus
= set_field(state
.mstatus
, MSTATUS32_SD
, dirty
);
608 state
.mstatus
= set_field(state
.mstatus
, MSTATUS64_SD
, dirty
);
610 state
.mstatus
= set_field(state
.mstatus
, MSTATUS_UXL
, xlen_to_uxl(max_xlen
));
611 state
.mstatus
= set_field(state
.mstatus
, MSTATUS_UXL
, xlen_to_uxl(max_xlen
));
612 state
.mstatus
= set_field(state
.mstatus
, MSTATUS_SXL
, xlen_to_uxl(max_xlen
));
613 // U-XLEN == S-XLEN == M-XLEN
618 reg_t mask
= MIP_SSIP
| MIP_STIP
;
619 state
.mip
= (state
.mip
& ~mask
) | (val
& mask
);
623 state
.mie
= (state
.mie
& ~all_ints
) | (val
& all_ints
);
626 state
.mideleg
= (state
.mideleg
& ~delegable_ints
) | (val
& delegable_ints
);
630 (1 << CAUSE_MISALIGNED_FETCH
) |
631 (1 << CAUSE_BREAKPOINT
) |
632 (1 << CAUSE_USER_ECALL
) |
633 (1 << CAUSE_FETCH_PAGE_FAULT
) |
634 (1 << CAUSE_LOAD_PAGE_FAULT
) |
635 (1 << CAUSE_STORE_PAGE_FAULT
);
636 state
.medeleg
= (state
.medeleg
& ~mask
) | (val
& mask
);
642 state
.minstret
= (state
.minstret
>> 32 << 32) | (val
& 0xffffffffU
);
644 state
.minstret
= val
;
645 // The ISA mandates that if an instruction writes instret, the write
646 // takes precedence over the increment to instret. However, Spike
647 // unconditionally increments instret after executing an instruction.
648 // Correct for this artifact by decrementing instret here.
653 state
.minstret
= (val
<< 32) | (state
.minstret
<< 32 >> 32);
654 state
.minstret
--; // See comment above.
657 state
.scounteren
= val
;
660 state
.mcounteren
= val
;
663 reg_t mask
= SSTATUS_SIE
| SSTATUS_SPIE
| SSTATUS_SPP
| SSTATUS_FS
664 | SSTATUS_XS
| SSTATUS_SUM
| SSTATUS_MXR
;
665 return set_csr(CSR_MSTATUS
, (state
.mstatus
& ~mask
) | (val
& mask
));
668 reg_t mask
= MIP_SSIP
& state
.mideleg
;
669 return set_csr(CSR_MIP
, (state
.mip
& ~mask
) | (val
& mask
));
672 return set_csr(CSR_MIE
,
673 (state
.mie
& ~state
.mideleg
) | (val
& state
.mideleg
));
677 state
.satp
= val
& (SATP32_PPN
| SATP32_MODE
);
678 if (max_xlen
== 64 && (get_field(val
, SATP64_MODE
) == SATP_MODE_OFF
||
679 get_field(val
, SATP64_MODE
) == SATP_MODE_SV39
||
680 get_field(val
, SATP64_MODE
) == SATP_MODE_SV48
))
681 state
.satp
= val
& (SATP64_PPN
| SATP64_MODE
);
684 case CSR_SEPC
: state
.sepc
= val
& ~(reg_t
)1; break;
685 case CSR_STVEC
: state
.stvec
= val
>> 2 << 2; break;
686 case CSR_SSCRATCH
: state
.sscratch
= val
; break;
687 case CSR_SCAUSE
: state
.scause
= val
; break;
688 case CSR_STVAL
: state
.stval
= val
; break;
689 case CSR_MEPC
: state
.mepc
= val
& ~(reg_t
)1; break;
690 case CSR_MTVEC
: state
.mtvec
= val
& ~(reg_t
)2; break;
691 case CSR_MSCRATCH
: state
.mscratch
= val
; break;
692 case CSR_MCAUSE
: state
.mcause
= val
; break;
693 case CSR_MTVAL
: state
.mtval
= val
; break;
695 // the write is ignored if increasing IALIGN would misalign the PC
696 if (!(val
& (1L << ('C' - 'A'))) && (state
.pc
& 2))
699 if (!(val
& (1L << ('F' - 'A'))))
700 val
&= ~(1L << ('D' - 'A'));
702 // allow MAFDC bits in MISA to be modified
704 mask
|= 1L << ('M' - 'A');
705 mask
|= 1L << ('A' - 'A');
706 mask
|= 1L << ('F' - 'A');
707 mask
|= 1L << ('D' - 'A');
708 mask
|= 1L << ('C' - 'A');
711 state
.misa
= (val
& mask
) | (state
.misa
& ~mask
);
715 if (val
< state
.num_triggers
) {
721 mcontrol_t
*mc
= &state
.mcontrol
[state
.tselect
];
722 if (mc
->dmode
&& !state
.dcsr
.cause
) {
725 mc
->dmode
= get_field(val
, MCONTROL_DMODE(xlen
));
726 mc
->select
= get_field(val
, MCONTROL_SELECT
);
727 mc
->timing
= get_field(val
, MCONTROL_TIMING
);
728 mc
->action
= (mcontrol_action_t
) get_field(val
, MCONTROL_ACTION
);
729 mc
->chain
= get_field(val
, MCONTROL_CHAIN
);
730 mc
->match
= (mcontrol_match_t
) get_field(val
, MCONTROL_MATCH
);
731 mc
->m
= get_field(val
, MCONTROL_M
);
732 mc
->h
= get_field(val
, MCONTROL_H
);
733 mc
->s
= get_field(val
, MCONTROL_S
);
734 mc
->u
= get_field(val
, MCONTROL_U
);
735 mc
->execute
= get_field(val
, MCONTROL_EXECUTE
);
736 mc
->store
= get_field(val
, MCONTROL_STORE
);
737 mc
->load
= get_field(val
, MCONTROL_LOAD
);
738 // Assume we're here because of csrw.
745 if (state
.mcontrol
[state
.tselect
].dmode
&& !state
.dcsr
.cause
) {
748 if (state
.tselect
< state
.num_triggers
) {
749 state
.tdata2
[state
.tselect
] = val
;
753 state
.dcsr
.prv
= get_field(val
, DCSR_PRV
);
754 state
.dcsr
.step
= get_field(val
, DCSR_STEP
);
755 // TODO: ndreset and fullreset
756 state
.dcsr
.ebreakm
= get_field(val
, DCSR_EBREAKM
);
757 state
.dcsr
.ebreakh
= get_field(val
, DCSR_EBREAKH
);
758 state
.dcsr
.ebreaks
= get_field(val
, DCSR_EBREAKS
);
759 state
.dcsr
.ebreaku
= get_field(val
, DCSR_EBREAKU
);
760 state
.dcsr
.halt
= get_field(val
, DCSR_HALT
);
763 state
.dpc
= val
& ~(reg_t
)1;
766 state
.dscratch
= val
;
771 reg_t
processor_t::get_csr(int which
)
773 uint32_t ctr_en
= -1;
774 if (state
.prv
< PRV_M
)
775 ctr_en
&= state
.mcounteren
;
776 if (state
.prv
< PRV_S
)
777 ctr_en
&= state
.scounteren
;
778 bool ctr_ok
= (ctr_en
>> (which
& 31)) & 1;
781 if (which
>= CSR_HPMCOUNTER3
&& which
<= CSR_HPMCOUNTER31
)
783 if (xlen
== 32 && which
>= CSR_HPMCOUNTER3H
&& which
<= CSR_HPMCOUNTER31H
)
786 if (which
>= CSR_MHPMCOUNTER3
&& which
<= CSR_MHPMCOUNTER31
)
788 if (xlen
== 32 && which
>= CSR_MHPMCOUNTER3H
&& which
<= CSR_MHPMCOUNTER31H
)
790 if (which
>= CSR_MHPMEVENT3
&& which
<= CSR_MHPMEVENT31
)
797 return state
.sv().vl
;
799 return (state
.sv().vl
-1) | ((state
.sv().mvl
-1)<<6) |
800 (state
.sv().srcoffs
<<12) | (state
.sv().destoffs
<<18) ;
802 return state
.sv().mvl
;
811 return 0;// XXX TODO: return correct entry
820 return 0;// XXX TODO: return correct entry
822 return 0;// XXX TODO: return correct entry
826 return 0;// XXX TODO: return correct entry
830 if (!supports_extension('F'))
835 if (!supports_extension('F'))
840 if (!supports_extension('F'))
842 return (state
.fflags
<< FSR_AEXC_SHIFT
) | (state
.frm
<< FSR_RD_SHIFT
);
846 return state
.minstret
;
850 return state
.minstret
;
853 if (ctr_ok
&& xlen
== 32)
854 return state
.minstret
>> 32;
859 return state
.minstret
>> 32;
861 case CSR_SCOUNTEREN
: return state
.scounteren
;
862 case CSR_MCOUNTEREN
: return state
.mcounteren
;
864 reg_t mask
= SSTATUS_SIE
| SSTATUS_SPIE
| SSTATUS_SPP
| SSTATUS_FS
865 | SSTATUS_XS
| SSTATUS_SUM
| SSTATUS_MXR
| SSTATUS_UXL
;
866 reg_t sstatus
= state
.mstatus
& mask
;
867 if ((sstatus
& SSTATUS_FS
) == SSTATUS_FS
||
868 (sstatus
& SSTATUS_XS
) == SSTATUS_XS
)
869 sstatus
|= (xlen
== 32 ? SSTATUS32_SD
: SSTATUS64_SD
);
872 case CSR_SIP
: return state
.mip
& state
.mideleg
;
873 case CSR_SIE
: return state
.mie
& state
.mideleg
;
874 case CSR_SEPC
: return state
.sepc
& pc_alignment_mask();
875 case CSR_STVAL
: return state
.stval
;
876 case CSR_STVEC
: return state
.stvec
;
879 return state
.scause
| ((state
.scause
>> (max_xlen
-1)) << (xlen
-1));
882 if (get_field(state
.mstatus
, MSTATUS_TVM
))
883 require_privilege(PRV_M
);
885 case CSR_SSCRATCH
: return state
.sscratch
;
886 case CSR_MSTATUS
: return state
.mstatus
;
887 case CSR_MIP
: return state
.mip
;
888 case CSR_MIE
: return state
.mie
;
889 case CSR_MEPC
: return state
.mepc
& pc_alignment_mask();
890 case CSR_MSCRATCH
: return state
.mscratch
;
891 case CSR_MCAUSE
: return state
.mcause
;
892 case CSR_MTVAL
: return state
.mtval
;
893 case CSR_MISA
: return state
.misa
;
894 case CSR_MARCHID
: return 0;
895 case CSR_MIMPID
: return 0;
896 case CSR_MVENDORID
: return 0;
897 case CSR_MHARTID
: return id
;
898 case CSR_MTVEC
: return state
.mtvec
;
899 case CSR_MEDELEG
: return state
.medeleg
;
900 case CSR_MIDELEG
: return state
.mideleg
;
901 case CSR_TSELECT
: return state
.tselect
;
903 if (state
.tselect
< state
.num_triggers
) {
905 mcontrol_t
*mc
= &state
.mcontrol
[state
.tselect
];
906 v
= set_field(v
, MCONTROL_TYPE(xlen
), mc
->type
);
907 v
= set_field(v
, MCONTROL_DMODE(xlen
), mc
->dmode
);
908 v
= set_field(v
, MCONTROL_MASKMAX(xlen
), mc
->maskmax
);
909 v
= set_field(v
, MCONTROL_SELECT
, mc
->select
);
910 v
= set_field(v
, MCONTROL_TIMING
, mc
->timing
);
911 v
= set_field(v
, MCONTROL_ACTION
, mc
->action
);
912 v
= set_field(v
, MCONTROL_CHAIN
, mc
->chain
);
913 v
= set_field(v
, MCONTROL_MATCH
, mc
->match
);
914 v
= set_field(v
, MCONTROL_M
, mc
->m
);
915 v
= set_field(v
, MCONTROL_H
, mc
->h
);
916 v
= set_field(v
, MCONTROL_S
, mc
->s
);
917 v
= set_field(v
, MCONTROL_U
, mc
->u
);
918 v
= set_field(v
, MCONTROL_EXECUTE
, mc
->execute
);
919 v
= set_field(v
, MCONTROL_STORE
, mc
->store
);
920 v
= set_field(v
, MCONTROL_LOAD
, mc
->load
);
927 if (state
.tselect
< state
.num_triggers
) {
928 return state
.tdata2
[state
.tselect
];
933 case CSR_TDATA3
: return 0;
937 v
= set_field(v
, DCSR_XDEBUGVER
, 1);
938 v
= set_field(v
, DCSR_EBREAKM
, state
.dcsr
.ebreakm
);
939 v
= set_field(v
, DCSR_EBREAKH
, state
.dcsr
.ebreakh
);
940 v
= set_field(v
, DCSR_EBREAKS
, state
.dcsr
.ebreaks
);
941 v
= set_field(v
, DCSR_EBREAKU
, state
.dcsr
.ebreaku
);
942 v
= set_field(v
, DCSR_STOPCYCLE
, 0);
943 v
= set_field(v
, DCSR_STOPTIME
, 0);
944 v
= set_field(v
, DCSR_CAUSE
, state
.dcsr
.cause
);
945 v
= set_field(v
, DCSR_STEP
, state
.dcsr
.step
);
946 v
= set_field(v
, DCSR_PRV
, state
.dcsr
.prv
);
950 return state
.dpc
& pc_alignment_mask();
952 return state
.dscratch
;
954 throw trap_illegal_instruction(0);
957 reg_t
illegal_instruction(processor_t
* p
, insn_t insn
, reg_t pc
)
959 throw trap_illegal_instruction(0);
962 insn_func_t
processor_t::decode_insn(insn_t insn
)
964 // look up opcode in hash table
965 size_t idx
= insn
.bits() % OPCODE_CACHE_SIZE
;
966 insn_desc_t desc
= opcode_cache
[idx
];
968 if (unlikely(insn
.bits() != desc
.match
)) {
969 // fall back to linear search
970 insn_desc_t
* p
= &instructions
[0];
971 while ((insn
.bits() & p
->mask
) != p
->match
)
975 if (p
->mask
!= 0 && p
> &instructions
[0]) {
976 if (p
->match
!= (p
-1)->match
&& p
->match
!= (p
+1)->match
) {
977 // move to front of opcode list to reduce miss penalty
978 while (--p
>= &instructions
[0])
980 instructions
[0] = desc
;
984 opcode_cache
[idx
] = desc
;
985 opcode_cache
[idx
].match
= insn
.bits();
988 return xlen
== 64 ? desc
.rv64
: desc
.rv32
;
991 void processor_t::register_insn(insn_desc_t desc
)
993 instructions
.push_back(desc
);
996 void processor_t::build_opcode_map()
999 bool operator()(const insn_desc_t
& lhs
, const insn_desc_t
& rhs
) {
1000 if (lhs
.match
== rhs
.match
)
1001 return lhs
.mask
> rhs
.mask
;
1002 return lhs
.match
> rhs
.match
;
1005 std::sort(instructions
.begin(), instructions
.end(), cmp());
1007 for (size_t i
= 0; i
< OPCODE_CACHE_SIZE
; i
++)
1008 opcode_cache
[i
] = {0, 0, &illegal_instruction
, &illegal_instruction
};
1011 void processor_t::register_extension(extension_t
* x
)
1013 for (auto insn
: x
->get_instructions())
1014 register_insn(insn
);
1016 for (auto disasm_insn
: x
->get_disasms())
1017 disassembler
->add_insn(disasm_insn
);
1019 throw std::logic_error("only one extension may be registered");
1021 x
->set_processor(this);
1024 void processor_t::register_base_instructions()
1026 #define DECLARE_INSN(name, match, mask) \
1027 insn_bits_t name##_match = (match), name##_mask = (mask);
1028 #include "encoding.h"
1031 #define DEFINE_INSN(name) \
1032 REGISTER_INSN(this, name, name##_match, name##_mask)
1033 #include "insn_list.h"
1036 register_insn({0, 0, &illegal_instruction
, &illegal_instruction
});
1040 bool processor_t::load(reg_t addr
, size_t len
, uint8_t* bytes
)
1046 memset(bytes
, 0, len
);
1047 bytes
[0] = get_field(state
.mip
, MIP_MSIP
);
1056 bool processor_t::store(reg_t addr
, size_t len
, const uint8_t* bytes
)
1062 state
.mip
= set_field(state
.mip
, MIP_MSIP
, bytes
[0]);
1071 void processor_t::trigger_updated()
1074 mmu
->check_triggers_fetch
= false;
1075 mmu
->check_triggers_load
= false;
1076 mmu
->check_triggers_store
= false;
1078 for (unsigned i
= 0; i
< state
.num_triggers
; i
++) {
1079 if (state
.mcontrol
[i
].execute
) {
1080 mmu
->check_triggers_fetch
= true;
1082 if (state
.mcontrol
[i
].load
) {
1083 mmu
->check_triggers_load
= true;
1085 if (state
.mcontrol
[i
].store
) {
1086 mmu
->check_triggers_store
= true;