riscv/processor.cc

   1 // See LICENSE for license details.
   2
   3 #include "processor.h"
   4 #include "extension.h"
   5 #include "common.h"
   6 #include "config.h"
   7 #include "sim.h"
   8 #include "htif.h"
   9 #include "disasm.h"
  10 #include "icache.h"
  11 #include <cinttypes>
  12 #include <cmath>
  13 #include <cstdlib>
  14 #include <iostream>
  15 #include <assert.h>
  16 #include <limits.h>
  17 #include <stdexcept>
  18 #include <algorithm>
  19
  20 processor_t::processor_t(sim_t* _sim, mmu_t* _mmu, uint32_t _id)
  21   : sim(_sim), mmu(_mmu), ext(NULL), disassembler(new disassembler_t),
  22     id(_id), run(false), debug(false)
  23 {
  24   reset(true);
  25   mmu->set_processor(this);
  26
  27   #define DECLARE_INSN(name, match, mask) REGISTER_INSN(this, name, match, mask)
  28   #include "encoding.h"
  29   #undef DECLARE_INSN
  30   build_opcode_map();
  31 }
  32
  33 processor_t::~processor_t()
  34 {
  35   delete disassembler;
  36 }
  37
  38 void state_t::reset()
  39 {
  40   // the ISA guarantees on boot that the PC is 0x2000 and the the processor
  41   // is in supervisor mode, and in 64-bit mode, if supported, with traps
  42   // and virtual memory disabled.
  43   sr = SR_S | SR_S64;
  44   pc = 0x2000;
  45
  46   // the following state is undefined upon boot-up,
  47   // but we zero it for determinism
  48   XPR.reset();
  49   FPR.reset();
  50
  51   epc = 0;
  52   badvaddr = 0;
  53   evec = 0;
  54   ptbr = 0;
  55   pcr_k0 = 0;
  56   pcr_k1 = 0;
  57   cause = 0;
  58   tohost = 0;
  59   fromhost = 0;
  60   count = 0;
  61   compare = 0;
  62   fflags = 0;
  63   frm = 0;
  64
  65   load_reservation = -1;
  66 }
  67
  68 void processor_t::set_debug(bool value)
  69 {
  70   debug = value;
  71   if (ext)
  72     ext->set_debug(value);
  73 }
  74
  75 void processor_t::reset(bool value)
  76 {
  77   if (run == !value)
  78     return;
  79   run = !value;
  80
  81   state.reset(); // reset the core
  82   set_pcr(CSR_STATUS, state.sr);
  83
  84   if (ext)
  85     ext->reset(); // reset the extension
  86 }
  87
  88 void processor_t::take_interrupt()
  89 {
  90   uint32_t interrupts = (state.sr & SR_IP) >> SR_IP_SHIFT;
  91   interrupts &= (state.sr & SR_IM) >> SR_IM_SHIFT;
  92
  93   if (interrupts && (state.sr & SR_EI))
  94     for (int i = 0; ; i++, interrupts >>= 1)
  95       if (interrupts & 1)
  96         throw trap_t((1ULL << ((state.sr & SR_S64) ? 63 : 31)) + i);
  97 }
  98
  99 static void commit_log(state_t* state, insn_t insn)
 100 {
 101 #ifdef RISCV_ENABLE_COMMITLOG
 102   if (!(state->sr & SR_S))
 103     fprintf(stderr, "\n0x%016" PRIx64 " (0x%08" PRIx32 ") ", state->pc, insn.bits());
 104 #endif
 105 }
 106
 107 void processor_t::step(size_t n)
 108 {
 109   if(!run)
 110     return;
 111
 112   mmu_t* _mmu = mmu;
 113   auto count32 = decltype(state.compare)(state.count);
 114   bool count_le_compare = count32 <= state.compare;
 115   n = std::min(n, size_t(state.compare - count32) | 1);
 116
 117   try
 118   {
 119     take_interrupt();
 120
 121     if (debug) // print out instructions as we go
 122     {
 123       for (size_t i = 0; i < n; state.count++, i++)
 124       {
 125         insn_fetch_t fetch = mmu->load_insn(state.pc);
 126         disasm(fetch.insn.insn);
 127         commit_log(&state, fetch.insn.insn);
 128         state.pc = fetch.func(this, fetch.insn.insn, state.pc);
 129       }
 130     }
 131     else while (n > 0)
 132     {
 133       size_t idx = (state.pc / sizeof(insn_t)) % ICACHE_SIZE;
 134       auto ic_entry = _mmu->access_icache(state.pc), ic_entry_init = ic_entry;
 135
 136       #define ICACHE_ACCESS(idx) { \
 137         insn_t insn = ic_entry->data.insn.insn; \
 138         insn_func_t func = ic_entry->data.func; \
 139         commit_log(&state, insn); \
 140         ic_entry++; \
 141         state.pc = func(this, insn, state.pc); \
 142         if (idx < ICACHE_SIZE-1 && unlikely(ic_entry->tag != state.pc)) break; \
 143       }
 144
 145       switch (idx)
 146       {
 147         ICACHE_SWITCH; // auto-generated into icache.h
 148       }
 149
 150       size_t i = ic_entry - ic_entry_init;
 151       state.count += i;
 152       if (i >= n)
 153         break;
 154       n -= i;
 155     }
 156   }
 157   catch(trap_t& t)
 158   {
 159     take_trap(t);
 160   }
 161
 162   bool count_ge_compare =
 163     uint64_t(n) + decltype(state.compare)(state.count) >= state.compare;
 164   if (count_le_compare && count_ge_compare)
 165     set_interrupt(IRQ_TIMER, true);
 166 }
 167
 168 void processor_t::take_trap(trap_t& t)
 169 {
 170   if (debug)
 171     fprintf(stderr, "core %3d: exception %s, epc 0x%016" PRIx64 "\n",
 172             id, t.name(), state.pc);
 173
 174   // switch to supervisor, set previous supervisor bit, disable interrupts
 175   set_pcr(CSR_STATUS, (((state.sr & ~SR_EI) | SR_S) & ~SR_PS & ~SR_PEI) |
 176                       ((state.sr & SR_S) ? SR_PS : 0) |
 177                       ((state.sr & SR_EI) ? SR_PEI : 0));
 178
 179   yield_load_reservation();
 180   state.cause = t.cause();
 181   state.epc = state.pc;
 182   state.pc = state.evec;
 183
 184   t.side_effects(&state); // might set badvaddr etc.
 185 }
 186
 187 void processor_t::deliver_ipi()
 188 {
 189   if (run)
 190     set_pcr(CSR_CLEAR_IPI, 1);
 191 }
 192
 193 void processor_t::disasm(insn_t insn)
 194 {
 195   // the disassembler is stateless, so we share it
 196   fprintf(stderr, "core %3d: 0x%016" PRIx64 " (0x%08" PRIx32 ") %s\n",
 197           id, state.pc, insn.bits(), disassembler->disassemble(insn).c_str());
 198 }
 199
 200 reg_t processor_t::set_pcr(int which, reg_t val)
 201 {
 202   reg_t old_pcr = get_pcr(which);
 203
 204   switch (which)
 205   {
 206     case CSR_FFLAGS:
 207       state.fflags = val & (FSR_AEXC >> FSR_AEXC_SHIFT);
 208       break;
 209     case CSR_FRM:
 210       state.frm = val & (FSR_RD >> FSR_RD_SHIFT);
 211       break;
 212     case CSR_FCSR:
 213       state.fflags = (val & FSR_AEXC) >> FSR_AEXC_SHIFT;
 214       state.frm = (val & FSR_RD) >> FSR_RD_SHIFT;
 215       break;
 216     case CSR_STATUS:
 217       state.sr = (val & ~SR_IP) | (state.sr & SR_IP);
 218 #ifndef RISCV_ENABLE_64BIT
 219       state.sr &= ~(SR_S64 | SR_U64);
 220 #endif
 221 #ifndef RISCV_ENABLE_FPU
 222       state.sr &= ~SR_EF;
 223 #endif
 224       if (!ext)
 225         state.sr &= ~SR_EA;
 226       state.sr &= ~SR_ZERO;
 227       rv64 = (state.sr & SR_S) ? (state.sr & SR_S64) : (state.sr & SR_U64);
 228       mmu->flush_tlb();
 229       break;
 230     case CSR_EPC:
 231       state.epc = val;
 232       break;
 233     case CSR_EVEC:
 234       state.evec = val & ~3;
 235       break;
 236     case CSR_CYCLE:
 237     case CSR_TIME:
 238     case CSR_INSTRET:
 239     case CSR_COUNT:
 240       state.count = val;
 241       break;
 242     case CSR_COMPARE:
 243       set_interrupt(IRQ_TIMER, false);
 244       state.compare = val;
 245       break;
 246     case CSR_PTBR:
 247       state.ptbr = val & ~(PGSIZE-1);
 248       break;
 249     case CSR_SEND_IPI:
 250       sim->send_ipi(val);
 251       break;
 252     case CSR_CLEAR_IPI:
 253       set_interrupt(IRQ_IPI, val & 1);
 254       break;
 255     case CSR_SUP0:
 256       state.pcr_k0 = val;
 257       break;
 258     case CSR_SUP1:
 259       state.pcr_k1 = val;
 260       break;
 261     case CSR_TOHOST:
 262       if (state.tohost == 0)
 263         state.tohost = val;
 264       break;
 265     case CSR_FROMHOST:
 266       set_fromhost(val);
 267       break;
 268   }
 269
 270   return old_pcr;
 271 }
 272
 273 void processor_t::set_fromhost(reg_t val)
 274 {
 275   set_interrupt(IRQ_HOST, val != 0);
 276   state.fromhost = val;
 277 }
 278
 279 reg_t processor_t::get_pcr(int which)
 280 {
 281   switch (which)
 282   {
 283     case CSR_FFLAGS:
 284       return state.fflags;
 285     case CSR_FRM:
 286       return state.frm;
 287     case CSR_FCSR:
 288       return (state.fflags << FSR_AEXC_SHIFT) | (state.frm << FSR_RD_SHIFT);
 289     case CSR_STATUS:
 290       return state.sr;
 291     case CSR_EPC:
 292       return state.epc;
 293     case CSR_BADVADDR:
 294       return state.badvaddr;
 295     case CSR_EVEC:
 296       return state.evec;
 297     case CSR_CYCLE:
 298     case CSR_TIME:
 299     case CSR_INSTRET:
 300     case CSR_COUNT:
 301       return state.count;
 302     case CSR_COMPARE:
 303       return state.compare;
 304     case CSR_CAUSE:
 305       return state.cause;
 306     case CSR_PTBR:
 307       return state.ptbr;
 308     case CSR_SEND_IPI:
 309     case CSR_CLEAR_IPI:
 310       return 0;
 311     case CSR_ASID:
 312       return 0;
 313     case CSR_FATC:
 314       mmu->flush_tlb();
 315       return 0;
 316     case CSR_HARTID:
 317       return id;
 318     case CSR_IMPL:
 319       return 1;
 320     case CSR_SUP0:
 321       return state.pcr_k0;
 322     case CSR_SUP1:
 323       return state.pcr_k1;
 324     case CSR_TOHOST:
 325       sim->get_htif()->tick(); // not necessary, but faster
 326       return state.tohost;
 327     case CSR_FROMHOST:
 328       sim->get_htif()->tick(); // not necessary, but faster
 329       return state.fromhost;
 330     default:
 331       throw trap_illegal_instruction();
 332   }
 333 }
 334
 335 void processor_t::set_interrupt(int which, bool on)
 336 {
 337   uint32_t mask = (1 << (which + SR_IP_SHIFT)) & SR_IP;
 338   if (on)
 339     state.sr |= mask;
 340   else
 341     state.sr &= ~mask;
 342 }
 343
 344 reg_t illegal_instruction(processor_t* p, insn_t insn, reg_t pc)
 345 {
 346   throw trap_illegal_instruction();
 347 }
 348
 349 insn_func_t processor_t::decode_insn(insn_t insn)
 350 {
 351   size_t mask = opcode_map.size()-1;
 352   insn_desc_t* desc = opcode_map[insn.bits() & mask];
 353
 354   while ((insn.bits() & desc->mask) != desc->match)
 355     desc++;
 356
 357   return rv64 ? desc->rv64 : desc->rv32;
 358 }
 359
 360 void processor_t::register_insn(insn_desc_t desc)
 361 {
 362   assert(desc.mask & 1);
 363   instructions.push_back(desc);
 364 }
 365
 366 void processor_t::build_opcode_map()
 367 {
 368   size_t buckets = -1;
 369   for (auto& inst : instructions)
 370     while ((inst.mask & buckets) != buckets)
 371       buckets /= 2;
 372   buckets++;
 373
 374   struct cmp {
 375     decltype(insn_desc_t::match) mask;
 376     cmp(decltype(mask) mask) : mask(mask) {}
 377     bool operator()(const insn_desc_t& lhs, const insn_desc_t& rhs) {
 378       if ((lhs.match & mask) != (rhs.match & mask))
 379         return (lhs.match & mask) < (rhs.match & mask);
 380       return lhs.match < rhs.match;
 381     }
 382   };
 383   std::sort(instructions.begin(), instructions.end(), cmp(buckets-1));
 384
 385   opcode_map.resize(buckets);
 386   opcode_store.resize(instructions.size() + 1);
 387
 388   size_t j = 0;
 389   for (size_t b = 0, i = 0; b < buckets; b++)
 390   {
 391     opcode_map[b] = &opcode_store[j];
 392     while (i < instructions.size() && b == (instructions[i].match & (buckets-1)))
 393       opcode_store[j++] = instructions[i++];
 394   }
 395
 396   assert(j == opcode_store.size()-1);
 397   opcode_store[j].match = opcode_store[j].mask = 0;
 398   opcode_store[j].rv32 = &illegal_instruction;
 399   opcode_store[j].rv64 = &illegal_instruction;
 400 }
 401
 402 void processor_t::register_extension(extension_t* x)
 403 {
 404   for (auto insn : x->get_instructions())
 405     register_insn(insn);
 406   build_opcode_map();
 407   for (auto disasm_insn : x->get_disasms())
 408     disassembler->add_insn(disasm_insn);
 409   if (ext != NULL)
 410     throw std::logic_error("only one extension may be registered");
 411   ext = x;
 412   x->set_processor(this);
 413 }