riscv/processor.cc

   1 #include "processor.h"
   2 #include "common.h"
   3 #include "config.h"
   4 #include "sim.h"
   5 #include "disasm.h"
   6 #include <inttypes.h>
   7 #include <cmath>
   8 #include <cstdlib>
   9 #include <iostream>
  10 #include <assert.h>
  11
  12 processor_t::processor_t(sim_t* _sim, mmu_t* _mmu, uint32_t _id)
  13   : sim(*_sim), mmu(*_mmu), id(_id), utidx(0)
  14 {
  15   reset(true);
  16
  17   // create microthreads
  18   for (int i=0; i<MAX_UTS; i++)
  19     uts[i] = new processor_t(&sim, &mmu, id, i);
  20 }
  21
  22 processor_t::processor_t(sim_t* _sim, mmu_t* _mmu, uint32_t _id,
  23                          uint32_t _utidx)
  24   : sim(*_sim), mmu(*_mmu), id(_id)
  25 {
  26   reset(true);
  27   set_pcr(PCR_SR, SR_U64 | SR_EF | SR_EV);
  28   utidx = _utidx;
  29
  30   // microthreads don't possess their own microthreads
  31   for (int i=0; i<MAX_UTS; i++)
  32     uts[i] = NULL;
  33 }
  34
  35 processor_t::~processor_t()
  36 {
  37 }
  38
  39 void processor_t::reset(bool value)
  40 {
  41   if (run == !value)
  42     return;
  43   run = !value;
  44
  45   // the ISA guarantees on boot that the PC is 0x2000 and the the processor
  46   // is in supervisor mode, and in 64-bit mode, if supported, with traps
  47   // and virtual memory disabled.
  48   set_pcr(PCR_SR, SR_S | SR_S64 | SR_IM);
  49   pc = 0x2000;
  50
  51   // the following state is undefined upon boot-up,
  52   // but we zero it for determinism
  53   XPR.reset();
  54   FPR.reset();
  55
  56   evec = 0;
  57   epc = 0;
  58   badvaddr = 0;
  59   cause = 0;
  60   pcr_k0 = 0;
  61   pcr_k1 = 0;
  62   count = 0;
  63   compare = 0;
  64   cycle = 0;
  65   set_fsr(0);
  66
  67   // vector stuff
  68   vecbanks = 0xff;
  69   vecbanks_count = 8;
  70   utidx = -1;
  71   vlmax = 32;
  72   vl = 0;
  73   nxfpr_bank = 256;
  74   nxpr_use = 32;
  75   nfpr_use = 32;
  76 }
  77
  78 void processor_t::set_fsr(uint32_t val)
  79 {
  80   fsr = val & ~FSR_ZERO; // clear FSR bits that read as zero
  81 }
  82
  83 void processor_t::vcfg()
  84 {
  85   if (nxpr_use + nfpr_use < 2)
  86     vlmax = nxfpr_bank * vecbanks_count;
  87   else
  88     vlmax = (nxfpr_bank / (nxpr_use + nfpr_use - 1)) * vecbanks_count;
  89
  90   vlmax = std::min(vlmax, MAX_UTS);
  91 }
  92
  93 void processor_t::setvl(int vlapp)
  94 {
  95   vl = std::min(vlmax, vlapp);
  96 }
  97
  98 void processor_t::take_interrupt()
  99 {
 100   uint32_t interrupts = (sr & SR_IP) >> SR_IP_SHIFT;
 101   interrupts &= (sr & SR_IM) >> SR_IM_SHIFT;
 102
 103   if(interrupts && (sr & SR_ET))
 104     for(int i = 0; ; i++, interrupts >>= 1)
 105       if(interrupts & 1)
 106         throw interrupt_t(i);
 107 }
 108
 109 void processor_t::step(size_t n, bool noisy)
 110 {
 111   if(!run)
 112     return;
 113
 114   size_t i = 0;
 115   try
 116   {
 117     take_interrupt();
 118
 119     mmu_t& _mmu = mmu;
 120     reg_t npc = pc;
 121
 122     // execute_insn fetches and executes one instruction
 123     #define execute_insn(noisy) \
 124       do { \
 125         mmu_t::insn_fetch_t fetch = _mmu.load_insn(npc, sr & SR_EC); \
 126         if(noisy) disasm(fetch.insn, npc); \
 127         npc = fetch.func(this, fetch.insn, npc); \
 128         pc = npc; \
 129       } while(0)
 130
 131     if(noisy) for( ; i < n; i++) // print out instructions as we go
 132       execute_insn(true);
 133     else
 134     {
 135       // unrolled for speed
 136       for( ; n > 3 && i < n-3; i+=4)
 137       {
 138         execute_insn(false);
 139         execute_insn(false);
 140         execute_insn(false);
 141         execute_insn(false);
 142       }
 143       for( ; i < n; i++)
 144         execute_insn(false);
 145     }
 146   }
 147   catch(trap_t t)
 148   {
 149     // an exception occurred in the target processor
 150     take_trap(t,noisy);
 151   }
 152   catch(interrupt_t t)
 153   {
 154     take_trap((1ULL << (8*sizeof(reg_t)-1)) + t.i, noisy);
 155   }
 156   catch(vt_command_t cmd)
 157   {
 158     // this microthread has finished
 159     assert(cmd == vt_command_stop);
 160   }
 161
 162   cycle += i;
 163
 164   // update timer and possibly register a timer interrupt
 165   uint32_t old_count = count;
 166   count += i;
 167   if(old_count < compare && uint64_t(old_count) + i >= compare)
 168     set_interrupt(IRQ_TIMER, true);
 169 }
 170
 171 void processor_t::take_trap(reg_t t, bool noisy)
 172 {
 173   if(noisy)
 174   {
 175     if ((sreg_t)t < 0)
 176       printf("core %3d: interrupt %lld, pc 0x%016llx\n",
 177              id, (long long)(t << 1 >> 1), (unsigned long long)pc);
 178     else
 179       printf("core %3d: trap %s, pc 0x%016llx\n",
 180              id, trap_name(trap_t(t)), (unsigned long long)pc);
 181   }
 182
 183   // switch to supervisor, set previous supervisor bit, disable traps
 184   set_pcr(PCR_SR, (((sr & ~SR_ET) | SR_S) & ~SR_PS) | ((sr & SR_S) ? SR_PS : 0));
 185   cause = t;
 186   epc = pc;
 187   pc = evec;
 188   badvaddr = mmu.get_badvaddr();
 189 }
 190
 191 void processor_t::deliver_ipi()
 192 {
 193   if (run)
 194     set_pcr(PCR_CLR_IPI, 1);
 195 }
 196
 197 void processor_t::disasm(insn_t insn, reg_t pc)
 198 {
 199   // the disassembler is stateless, so we share it
 200   static disassembler disasm;
 201   printf("core %3d: 0x%016llx (0x%08x) %s\n", id, (unsigned long long)pc,
 202          insn.bits, disasm.disassemble(insn).c_str());
 203 }
 204
 205 void processor_t::set_pcr(int which, reg_t val)
 206 {
 207   switch (which)
 208   {
 209     case PCR_SR:
 210       sr = val & ~SR_ZERO; // clear SR bits that read as zero
 211 #ifndef RISCV_ENABLE_64BIT
 212       sr &= ~(SR_S64 | SR_U64);
 213 #endif
 214 #ifndef RISCV_ENABLE_FPU
 215       sr &= ~SR_EF;
 216 #endif
 217 #ifndef RISCV_ENABLE_RVC
 218       sr &= ~SR_EC;
 219 #endif
 220 #ifndef RISCV_ENABLE_VEC
 221       sr &= ~SR_EV;
 222 #endif
 223       // update MMU state and flush TLB
 224       mmu.set_vm_enabled(sr & SR_VM);
 225       mmu.set_supervisor(sr & SR_S);
 226       mmu.flush_tlb();
 227       // set the fixed-point register length
 228       xprlen = ((sr & SR_S) ? (sr & SR_S64) : (sr & SR_U64)) ? 64 : 32;
 229       break;
 230     case PCR_EPC:
 231       epc = val;
 232       break;
 233     case PCR_EVEC:
 234       evec = val;
 235       break;
 236     case PCR_COUNT:
 237       count = val;
 238       break;
 239     case PCR_COMPARE:
 240       set_interrupt(IRQ_TIMER, false);
 241       compare = val;
 242       break;
 243     case PCR_PTBR:
 244       mmu.set_ptbr(val);
 245       break;
 246     case PCR_SEND_IPI:
 247       sim.send_ipi(val);
 248       break;
 249     case PCR_CLR_IPI:
 250       set_interrupt(IRQ_IPI, val & 1);
 251       break;
 252     case PCR_K0:
 253       pcr_k0 = val;
 254       break;
 255     case PCR_K1:
 256       pcr_k1 = val;
 257       break;
 258     case PCR_VECBANK:
 259       vecbanks = val & 0xff;
 260       vecbanks_count = __builtin_popcountll(vecbanks);
 261       break;
 262     case PCR_TOHOST:
 263       if (tohost == 0)
 264         tohost = val;
 265       break;
 266     case PCR_FROMHOST:
 267       set_interrupt(IRQ_HOST, val != 0);
 268       fromhost = val;
 269       break;
 270   }
 271 }
 272
 273 reg_t processor_t::get_pcr(int which)
 274 {
 275   switch (which)
 276   {
 277     case PCR_SR:
 278       return sr;
 279     case PCR_EPC:
 280       return epc;
 281     case PCR_BADVADDR:
 282       return badvaddr;
 283     case PCR_EVEC:
 284       return evec;
 285     case PCR_COUNT:
 286       return count;
 287     case PCR_COMPARE:
 288       return compare;
 289     case PCR_CAUSE:
 290       return cause;
 291     case PCR_PTBR:
 292       return mmu.get_ptbr();
 293     case PCR_COREID:
 294       return id;
 295     case PCR_IMPL:
 296       return 1;
 297     case PCR_K0:
 298       return pcr_k0;
 299     case PCR_K1:
 300       return pcr_k1;
 301     case PCR_VECBANK:
 302       return vecbanks;
 303     case PCR_TOHOST:
 304       return tohost;
 305     case PCR_FROMHOST:
 306       return fromhost;
 307   }
 308   return -1;
 309 }
 310
 311 void processor_t::set_interrupt(int which, bool on)
 312 {
 313   uint32_t mask = (1 << (which + SR_IP_SHIFT)) & SR_IP;
 314   if (on)
 315     sr |= mask;
 316   else
 317     sr &= ~mask;
 318 }