1 // See LICENSE for license details.
19 #include "sv_insn_redirect.h"
25 processor_t::processor_t(const char* isa
, simif_t
* sim
, uint32_t id
,
27 : debug(false), halt_request(false), sim(sim
), ext(NULL
), id(id
),
28 halt_on_reset(halt_on_reset
), last_pc(1), executions(1)
33 parse_isa_string(isa
);
34 register_base_instructions();
37 mmu
= new sv_mmu_t(sim
, this);
39 mmu
= new mmu_t(sim
, this);
42 disassembler
= new disassembler_t(max_xlen
);
44 for (auto disasm_insn
: ext
->get_disasms())
45 disassembler
->add_insn(disasm_insn
);
50 processor_t::~processor_t()
52 #ifdef RISCV_ENABLE_HISTOGRAM
53 if (histogram_enabled
)
55 fprintf(stderr
, "PC Histogram size:%zu\n", pc_histogram
.size());
56 for (auto it
: pc_histogram
)
57 fprintf(stderr
, "%0" PRIx64
" %" PRIu64
"\n", it
.first
, it
.second
);
65 static void bad_isa_string(const char* isa
)
67 fprintf(stderr
, "error: bad --isa option %s\n", isa
);
71 void processor_t::parse_isa_string(const char* str
)
73 std::string lowercase
, tmp
;
74 for (const char *r
= str
; *r
; r
++)
75 lowercase
+= std::tolower(*r
);
77 const char* p
= lowercase
.c_str();
78 const char* all_subsets
= "imafdqc";
81 state
.misa
= reg_t(2) << 62;
83 if (strncmp(p
, "rv32", 4) == 0)
84 max_xlen
= 32, state
.misa
= reg_t(1) << 30, p
+= 4;
85 else if (strncmp(p
, "rv64", 4) == 0)
87 else if (strncmp(p
, "rv", 2) == 0)
92 } else if (*p
== 'g') { // treat "G" as "IMAFD"
93 tmp
= std::string("imafd") + (p
+1);
95 } else if (*p
!= 'i') {
99 isa_string
= "rv" + std::to_string(max_xlen
) + p
;
100 state
.misa
|= 1L << ('s' - 'a'); // advertise support for supervisor mode
101 state
.misa
|= 1L << ('u' - 'a'); // advertise support for user mode
104 state
.misa
|= 1L << (*p
- 'a');
106 if (auto next
= strchr(all_subsets
, *p
)) {
107 all_subsets
= next
+ 1;
109 } else if (*p
== 'x') {
110 const char* ext
= p
+1, *end
= ext
;
111 while (islower(*end
))
113 register_extension(find_extension(std::string(ext
, end
- ext
).c_str())());
120 if (supports_extension('D') && !supports_extension('F'))
123 if (supports_extension('Q') && !supports_extension('D'))
126 if (supports_extension('Q') && max_xlen
< 64)
129 max_isa
= state
.misa
;
132 void state_t::reset(reg_t max_isa
)
134 memset(this, 0, sizeof(*this));
139 for (unsigned int i
= 0; i
< num_triggers
; i
++)
140 mcontrol
[i
].type
= 2;
143 int state_t::sv_csr_sz()
151 sv_csr_t
&state_t::sv()
160 void processor_t::set_debug(bool value
)
164 ext
->set_debug(value
);
167 void processor_t::set_histogram(bool value
)
169 histogram_enabled
= value
;
170 #ifndef RISCV_ENABLE_HISTOGRAM
172 fprintf(stderr
, "PC Histogram support has not been properly enabled;");
173 fprintf(stderr
, " please re-build the riscv-isa-run project using \"configure --enable-histogram\".\n");
178 void processor_t::reset()
180 state
.reset(max_isa
);
181 state
.dcsr
.halt
= halt_on_reset
;
182 halt_on_reset
= false;
183 set_csr(CSR_MSTATUS
, state
.mstatus
);
186 ext
->reset(); // reset the extension
192 // Count number of contiguous 0 bits starting from the LSB.
193 static int ctz(reg_t val
)
197 while ((val
& 1) == 0)
202 void processor_t::take_interrupt(reg_t pending_interrupts
)
204 reg_t mie
= get_field(state
.mstatus
, MSTATUS_MIE
);
205 reg_t m_enabled
= state
.prv
< PRV_M
|| (state
.prv
== PRV_M
&& mie
);
206 reg_t enabled_interrupts
= pending_interrupts
& ~state
.mideleg
& -m_enabled
;
208 reg_t sie
= get_field(state
.mstatus
, MSTATUS_SIE
);
209 reg_t s_enabled
= state
.prv
< PRV_S
|| (state
.prv
== PRV_S
&& sie
);
210 // M-ints have highest priority; consider S-ints only if no M-ints pending
211 if (enabled_interrupts
== 0)
212 enabled_interrupts
= pending_interrupts
& state
.mideleg
& -s_enabled
;
214 if (state
.dcsr
.cause
== 0 && enabled_interrupts
) {
215 // nonstandard interrupts have highest priority
216 if (enabled_interrupts
>> IRQ_M_EXT
)
217 enabled_interrupts
= enabled_interrupts
>> IRQ_M_EXT
<< IRQ_M_EXT
;
218 // external interrupts have next-highest priority
219 else if (enabled_interrupts
& (MIP_MEIP
| MIP_SEIP
))
220 enabled_interrupts
= enabled_interrupts
& (MIP_MEIP
| MIP_SEIP
);
221 // software interrupts have next-highest priority
222 else if (enabled_interrupts
& (MIP_MSIP
| MIP_SSIP
))
223 enabled_interrupts
= enabled_interrupts
& (MIP_MSIP
| MIP_SSIP
);
224 // timer interrupts have next-highest priority
225 else if (enabled_interrupts
& (MIP_MTIP
| MIP_STIP
))
226 enabled_interrupts
= enabled_interrupts
& (MIP_MTIP
| MIP_STIP
);
230 throw trap_t(((reg_t
)1 << (max_xlen
-1)) | ctz(enabled_interrupts
));
234 static int xlen_to_uxl(int xlen
)
243 reg_t
processor_t::legalize_privilege(reg_t prv
)
245 assert(prv
<= PRV_M
);
247 if (!supports_extension('U'))
250 if (prv
== PRV_H
|| !supports_extension('S'))
256 void processor_t::set_privilege(reg_t prv
)
259 state
.prv
= legalize_privilege(prv
);
262 void processor_t::enter_debug_mode(uint8_t cause
)
264 state
.dcsr
.cause
= cause
;
265 state
.dcsr
.prv
= state
.prv
;
266 set_privilege(PRV_M
);
267 state
.dpc
= state
.pc
;
268 state
.pc
= DEBUG_ROM_ENTRY
;
271 void processor_t::take_trap(trap_t
& t
, reg_t epc
)
274 fprintf(stderr
, "core %3d: exception %s, epc 0x%016" PRIx64
"\n",
277 fprintf(stderr
, "core %3d: tval 0x%016" PRIx64
"\n", id
,
281 if (state
.dcsr
.cause
) {
282 if (t
.cause() == CAUSE_BREAKPOINT
) {
283 state
.pc
= DEBUG_ROM_ENTRY
;
285 state
.pc
= DEBUG_ROM_TVEC
;
290 if (t
.cause() == CAUSE_BREAKPOINT
&& (
291 (state
.prv
== PRV_M
&& state
.dcsr
.ebreakm
) ||
292 (state
.prv
== PRV_S
&& state
.dcsr
.ebreaks
) ||
293 (state
.prv
== PRV_U
&& state
.dcsr
.ebreaku
))) {
294 enter_debug_mode(DCSR_CAUSE_SWBP
);
298 // by default, trap to M-mode, unless delegated to S-mode
299 reg_t bit
= t
.cause();
300 reg_t deleg
= state
.medeleg
;
301 bool interrupt
= (bit
& ((reg_t
)1 << (max_xlen
-1))) != 0;
303 deleg
= state
.mideleg
, bit
&= ~((reg_t
)1 << (max_xlen
-1));
304 if (state
.prv
<= PRV_S
&& bit
< max_xlen
&& ((deleg
>> bit
) & 1)) {
305 // handle the trap in S-mode
306 state
.pc
= state
.stvec
;
307 state
.scause
= t
.cause();
309 state
.stval
= t
.get_tval();
311 reg_t s
= state
.mstatus
;
312 s
= set_field(s
, MSTATUS_SPIE
, get_field(s
, MSTATUS_SIE
));
313 s
= set_field(s
, MSTATUS_SPP
, state
.prv
);
314 s
= set_field(s
, MSTATUS_SIE
, 0);
315 set_csr(CSR_MSTATUS
, s
);
316 set_privilege(PRV_S
);
318 reg_t vector
= (state
.mtvec
& 1) && interrupt
? 4*bit
: 0;
319 state
.pc
= (state
.mtvec
& ~(reg_t
)1) + vector
;
321 state
.mcause
= t
.cause();
322 state
.mtval
= t
.get_tval();
324 reg_t s
= state
.mstatus
;
325 s
= set_field(s
, MSTATUS_MPIE
, get_field(s
, MSTATUS_MIE
));
326 s
= set_field(s
, MSTATUS_MPP
, state
.prv
);
327 s
= set_field(s
, MSTATUS_MIE
, 0);
328 set_csr(CSR_MSTATUS
, s
);
329 set_privilege(PRV_M
);
333 void processor_t::disasm(insn_t insn
)
335 uint64_t bits
= insn
.bits() & ((1ULL << (8 * insn_length(insn
.bits()))) - 1);
336 if (last_pc
!= state
.pc
|| last_bits
!= bits
) {
337 if (executions
!= 1) {
338 fprintf(stderr
, "core %3d: Executed %" PRIx64
" times\n", id
, executions
);
341 fprintf(stderr
, "core %3d: 0x%016" PRIx64
" (0x%08" PRIx64
") %s\n",
342 id
, state
.pc
, bits
, disassembler
->disassemble(insn
).c_str());
351 int processor_t::paddr_bits()
353 assert(xlen
== max_xlen
);
354 return max_xlen
== 64 ? 50 : 34;
357 void processor_t::set_csr(int which
, reg_t val
)
359 val
= _zext_xlen(val
);
360 reg_t delegable_ints
= MIP_SSIP
| MIP_STIP
| MIP_SEIP
361 | ((ext
!= NULL
) << IRQ_COP
);
362 reg_t all_ints
= delegable_ints
| MIP_MSIP
| MIP_MTIP
;
363 fprintf(stderr
, "set CSR %x %lx\n", which
, val
);
368 state
.sv().mvl
= std::min(val
, (uint64_t)64); // limited to XLEN width
369 // TODO XXX throw exception if val == 0
370 fprintf(stderr
, "set MVL %lx\n", state
.sv().mvl
);
373 // bits 0-5: mvl - 6-11: vl - 12-17: srcoffs - 18-23: destoffs
374 set_csr(CSR_USVMVL
, get_field(val
, 0x1f )+1);
375 set_csr(CSR_USVVL
, get_field(val
, 0x1f<<6)+1);
376 state
.sv().srcoffs
= std::min(get_field(val
, 0x1f<<12), state
.sv().vl
-1);
377 state
.sv().destoffs
= std::min(get_field(val
, 0x1f<<18), state
.sv().vl
-1);
380 state
.sv().vl
= std::min(state
.sv().mvl
, val
);
381 // TODO XXX throw exception if val == 0
382 fprintf(stderr
, "set VL %lx\n", state
.sv().vl
);
393 uint64_t v
= (uint64_t)val
;
394 // identify which (pair) of SV config CAM registers are being set
395 int tbidx
= (which
- CSR_SVREGCFG0
) * 2;
396 fprintf(stderr
, "set REGCFG %d %lx\n", tbidx
, v
);
397 // lower 16 bits go into even, upper into odd...
398 state
.sv().sv_csrs
[tbidx
].u
= get_field(v
, 0xffffUL
);
399 state
.sv().sv_csrs
[tbidx
+1].u
= get_field(v
, 0xffffUL
<<16);
403 state
.sv().sv_csrs
[tbidx
+2].u
= get_field(v
, 0xffffUL
<<32);
404 state
.sv().sv_csrs
[tbidx
+3].u
= get_field(v
, 0xffffUL
<<48);
407 // clear out all CSRs above the one(s) being set: this ensures that
408 // when it comes to context-switching, it's clear what needs to be saved
409 for (int i
= tbidx
+clroffset
; i
< 16; i
++)
411 fprintf(stderr
, "clr REGCFG %d\n", i
);
412 state
.sv().sv_csrs
[i
].u
= 0;
414 // okaaay and now "unpack" the CAM to make it easier to use. this
415 // approach is not designed to be efficient right now. optimise later
416 // first clear the old tables
417 memset(state
.sv().sv_int_tb
, 0, sizeof(state
.sv().sv_int_tb
));
418 memset(state
.sv().sv_fp_tb
, 0, sizeof(state
.sv().sv_fp_tb
));
419 // now walk the CAM and unpack it
420 for (int i
= 0; i
< state
.sv_csr_sz(); i
++)
422 union sv_reg_csr_entry
*c
= &state
.sv().sv_csrs
[i
];
423 uint64_t idx
= c
->b
.regkey
;
429 // XXX damn. this basically duplicates sv_insn_t::get_regentry.
432 r
= &state
.sv().sv_int_tb
[idx
];
436 r
= &state
.sv().sv_fp_tb
[idx
];
438 r
->elwidth
= c
->b
.elwidth
;
439 r
->regidx
= c
->b
.regidx
;
440 r
->isvec
= c
->b
.isvec
;
442 fprintf(stderr
, "setting REGCFG type:%d isvec:%d %d %d\n",
443 c
->b
.type
, r
->isvec
, (int)idx
, (int)r
->regidx
);
456 // comments removed as it's near-identical to the regs version
458 uint64_t v
= (uint64_t)val
;
459 int tbidx
= (which
- CSR_SVPREDCFG0
) * 2;
460 fprintf(stderr
, "set PREDCFG %d %lx\n", tbidx
, v
);
461 state
.sv().sv_pred_csrs
[tbidx
].u
= get_field(v
, 0xffff);
462 state
.sv().sv_pred_csrs
[tbidx
+1].u
= get_field(v
, 0xffff0000);
466 state
.sv().sv_pred_csrs
[tbidx
+2].u
= get_field(v
, 0xffffUL
<<32);
467 state
.sv().sv_pred_csrs
[tbidx
+3].u
= get_field(v
, 0xffffUL
<<48);
470 for (int i
= tbidx
+clroffset
; i
< 16; i
++)
472 state
.sv().sv_pred_csrs
[i
].u
= 0;
474 memset(state
.sv().sv_pred_int_tb
, 0, sizeof(state
.sv().sv_pred_int_tb
));
475 memset(state
.sv().sv_pred_fp_tb
, 0, sizeof(state
.sv().sv_pred_fp_tb
));
476 for (int i
= 0; i
< state
.sv_csr_sz(); i
++)
478 union sv_pred_csr_entry
*c
= &state
.sv().sv_pred_csrs
[i
];
479 uint64_t idx
= c
->b
.regkey
;
485 // XXX damn. this basically duplicates sv_insn_t::get_predentry.
488 r
= &state
.sv().sv_pred_int_tb
[idx
];
492 r
= &state
.sv().sv_pred_fp_tb
[idx
];
494 r
->regidx
= c
->b
.regidx
;
497 r
->packed
= c
->b
.packed
;
499 fprintf(stderr
, "setting PREDCFG %d type:%d zero:%d %d %d\n",
500 i
, c
->b
.type
, r
->zero
, (int)idx
, (int)r
->regidx
);
507 state
.fflags
= val
& (FSR_AEXC
>> FSR_AEXC_SHIFT
);
511 state
.frm
= val
& (FSR_RD
>> FSR_RD_SHIFT
);
515 state
.fflags
= (val
& FSR_AEXC
) >> FSR_AEXC_SHIFT
;
516 state
.frm
= (val
& FSR_RD
) >> FSR_RD_SHIFT
;
519 if ((val
^ state
.mstatus
) &
520 (MSTATUS_MPP
| MSTATUS_MPRV
| MSTATUS_SUM
| MSTATUS_MXR
))
523 reg_t mask
= MSTATUS_SIE
| MSTATUS_SPIE
| MSTATUS_MIE
| MSTATUS_MPIE
524 | MSTATUS_FS
| MSTATUS_MPRV
| MSTATUS_SUM
525 | MSTATUS_MXR
| MSTATUS_TW
| MSTATUS_TVM
526 | MSTATUS_TSR
| MSTATUS_UXL
| MSTATUS_SXL
|
527 (ext
? MSTATUS_XS
: 0);
529 reg_t requested_mpp
= legalize_privilege(get_field(val
, MSTATUS_MPP
));
530 state
.mstatus
= set_field(state
.mstatus
, MSTATUS_MPP
, requested_mpp
);
531 if (supports_extension('S'))
534 state
.mstatus
= (state
.mstatus
& ~mask
) | (val
& mask
);
536 bool dirty
= (state
.mstatus
& MSTATUS_FS
) == MSTATUS_FS
;
537 dirty
|= (state
.mstatus
& MSTATUS_XS
) == MSTATUS_XS
;
539 state
.mstatus
= set_field(state
.mstatus
, MSTATUS32_SD
, dirty
);
541 state
.mstatus
= set_field(state
.mstatus
, MSTATUS64_SD
, dirty
);
543 state
.mstatus
= set_field(state
.mstatus
, MSTATUS_UXL
, xlen_to_uxl(max_xlen
));
544 state
.mstatus
= set_field(state
.mstatus
, MSTATUS_UXL
, xlen_to_uxl(max_xlen
));
545 state
.mstatus
= set_field(state
.mstatus
, MSTATUS_SXL
, xlen_to_uxl(max_xlen
));
546 // U-XLEN == S-XLEN == M-XLEN
551 reg_t mask
= MIP_SSIP
| MIP_STIP
;
552 state
.mip
= (state
.mip
& ~mask
) | (val
& mask
);
556 state
.mie
= (state
.mie
& ~all_ints
) | (val
& all_ints
);
559 state
.mideleg
= (state
.mideleg
& ~delegable_ints
) | (val
& delegable_ints
);
563 (1 << CAUSE_MISALIGNED_FETCH
) |
564 (1 << CAUSE_BREAKPOINT
) |
565 (1 << CAUSE_USER_ECALL
) |
566 (1 << CAUSE_FETCH_PAGE_FAULT
) |
567 (1 << CAUSE_LOAD_PAGE_FAULT
) |
568 (1 << CAUSE_STORE_PAGE_FAULT
);
569 state
.medeleg
= (state
.medeleg
& ~mask
) | (val
& mask
);
575 state
.minstret
= (state
.minstret
>> 32 << 32) | (val
& 0xffffffffU
);
577 state
.minstret
= val
;
578 // The ISA mandates that if an instruction writes instret, the write
579 // takes precedence over the increment to instret. However, Spike
580 // unconditionally increments instret after executing an instruction.
581 // Correct for this artifact by decrementing instret here.
586 state
.minstret
= (val
<< 32) | (state
.minstret
<< 32 >> 32);
587 state
.minstret
--; // See comment above.
590 state
.scounteren
= val
;
593 state
.mcounteren
= val
;
596 reg_t mask
= SSTATUS_SIE
| SSTATUS_SPIE
| SSTATUS_SPP
| SSTATUS_FS
597 | SSTATUS_XS
| SSTATUS_SUM
| SSTATUS_MXR
;
598 return set_csr(CSR_MSTATUS
, (state
.mstatus
& ~mask
) | (val
& mask
));
601 reg_t mask
= MIP_SSIP
& state
.mideleg
;
602 return set_csr(CSR_MIP
, (state
.mip
& ~mask
) | (val
& mask
));
605 return set_csr(CSR_MIE
,
606 (state
.mie
& ~state
.mideleg
) | (val
& state
.mideleg
));
610 state
.satp
= val
& (SATP32_PPN
| SATP32_MODE
);
611 if (max_xlen
== 64 && (get_field(val
, SATP64_MODE
) == SATP_MODE_OFF
||
612 get_field(val
, SATP64_MODE
) == SATP_MODE_SV39
||
613 get_field(val
, SATP64_MODE
) == SATP_MODE_SV48
))
614 state
.satp
= val
& (SATP64_PPN
| SATP64_MODE
);
617 case CSR_SEPC
: state
.sepc
= val
& ~(reg_t
)1; break;
618 case CSR_STVEC
: state
.stvec
= val
>> 2 << 2; break;
619 case CSR_SSCRATCH
: state
.sscratch
= val
; break;
620 case CSR_SCAUSE
: state
.scause
= val
; break;
621 case CSR_STVAL
: state
.stval
= val
; break;
622 case CSR_MEPC
: state
.mepc
= val
& ~(reg_t
)1; break;
623 case CSR_MTVEC
: state
.mtvec
= val
& ~(reg_t
)2; break;
624 case CSR_MSCRATCH
: state
.mscratch
= val
; break;
625 case CSR_MCAUSE
: state
.mcause
= val
; break;
626 case CSR_MTVAL
: state
.mtval
= val
; break;
628 // the write is ignored if increasing IALIGN would misalign the PC
629 if (!(val
& (1L << ('C' - 'A'))) && (state
.pc
& 2))
632 if (!(val
& (1L << ('F' - 'A'))))
633 val
&= ~(1L << ('D' - 'A'));
635 // allow MAFDC bits in MISA to be modified
637 mask
|= 1L << ('M' - 'A');
638 mask
|= 1L << ('A' - 'A');
639 mask
|= 1L << ('F' - 'A');
640 mask
|= 1L << ('D' - 'A');
641 mask
|= 1L << ('C' - 'A');
644 state
.misa
= (val
& mask
) | (state
.misa
& ~mask
);
648 if (val
< state
.num_triggers
) {
654 mcontrol_t
*mc
= &state
.mcontrol
[state
.tselect
];
655 if (mc
->dmode
&& !state
.dcsr
.cause
) {
658 mc
->dmode
= get_field(val
, MCONTROL_DMODE(xlen
));
659 mc
->select
= get_field(val
, MCONTROL_SELECT
);
660 mc
->timing
= get_field(val
, MCONTROL_TIMING
);
661 mc
->action
= (mcontrol_action_t
) get_field(val
, MCONTROL_ACTION
);
662 mc
->chain
= get_field(val
, MCONTROL_CHAIN
);
663 mc
->match
= (mcontrol_match_t
) get_field(val
, MCONTROL_MATCH
);
664 mc
->m
= get_field(val
, MCONTROL_M
);
665 mc
->h
= get_field(val
, MCONTROL_H
);
666 mc
->s
= get_field(val
, MCONTROL_S
);
667 mc
->u
= get_field(val
, MCONTROL_U
);
668 mc
->execute
= get_field(val
, MCONTROL_EXECUTE
);
669 mc
->store
= get_field(val
, MCONTROL_STORE
);
670 mc
->load
= get_field(val
, MCONTROL_LOAD
);
671 // Assume we're here because of csrw.
678 if (state
.mcontrol
[state
.tselect
].dmode
&& !state
.dcsr
.cause
) {
681 if (state
.tselect
< state
.num_triggers
) {
682 state
.tdata2
[state
.tselect
] = val
;
686 state
.dcsr
.prv
= get_field(val
, DCSR_PRV
);
687 state
.dcsr
.step
= get_field(val
, DCSR_STEP
);
688 // TODO: ndreset and fullreset
689 state
.dcsr
.ebreakm
= get_field(val
, DCSR_EBREAKM
);
690 state
.dcsr
.ebreakh
= get_field(val
, DCSR_EBREAKH
);
691 state
.dcsr
.ebreaks
= get_field(val
, DCSR_EBREAKS
);
692 state
.dcsr
.ebreaku
= get_field(val
, DCSR_EBREAKU
);
693 state
.dcsr
.halt
= get_field(val
, DCSR_HALT
);
696 state
.dpc
= val
& ~(reg_t
)1;
699 state
.dscratch
= val
;
704 reg_t
processor_t::get_csr(int which
)
706 uint32_t ctr_en
= -1;
707 if (state
.prv
< PRV_M
)
708 ctr_en
&= state
.mcounteren
;
709 if (state
.prv
< PRV_S
)
710 ctr_en
&= state
.scounteren
;
711 bool ctr_ok
= (ctr_en
>> (which
& 31)) & 1;
714 if (which
>= CSR_HPMCOUNTER3
&& which
<= CSR_HPMCOUNTER31
)
716 if (xlen
== 32 && which
>= CSR_HPMCOUNTER3H
&& which
<= CSR_HPMCOUNTER31H
)
719 if (which
>= CSR_MHPMCOUNTER3
&& which
<= CSR_MHPMCOUNTER31
)
721 if (xlen
== 32 && which
>= CSR_MHPMCOUNTER3H
&& which
<= CSR_MHPMCOUNTER31H
)
723 if (which
>= CSR_MHPMEVENT3
&& which
<= CSR_MHPMEVENT31
)
730 return state
.sv().vl
;
732 return (state
.sv().vl
-1) | ((state
.sv().mvl
-1)<<6) |
733 (state
.sv().srcoffs
<<12) | (state
.sv().destoffs
<<18) ;
735 return state
.sv().mvl
;
744 return 0;// XXX TODO: return correct entry
753 return 0;// XXX TODO: return correct entry
757 if (!supports_extension('F'))
762 if (!supports_extension('F'))
767 if (!supports_extension('F'))
769 return (state
.fflags
<< FSR_AEXC_SHIFT
) | (state
.frm
<< FSR_RD_SHIFT
);
773 return state
.minstret
;
777 return state
.minstret
;
780 if (ctr_ok
&& xlen
== 32)
781 return state
.minstret
>> 32;
786 return state
.minstret
>> 32;
788 case CSR_SCOUNTEREN
: return state
.scounteren
;
789 case CSR_MCOUNTEREN
: return state
.mcounteren
;
791 reg_t mask
= SSTATUS_SIE
| SSTATUS_SPIE
| SSTATUS_SPP
| SSTATUS_FS
792 | SSTATUS_XS
| SSTATUS_SUM
| SSTATUS_MXR
| SSTATUS_UXL
;
793 reg_t sstatus
= state
.mstatus
& mask
;
794 if ((sstatus
& SSTATUS_FS
) == SSTATUS_FS
||
795 (sstatus
& SSTATUS_XS
) == SSTATUS_XS
)
796 sstatus
|= (xlen
== 32 ? SSTATUS32_SD
: SSTATUS64_SD
);
799 case CSR_SIP
: return state
.mip
& state
.mideleg
;
800 case CSR_SIE
: return state
.mie
& state
.mideleg
;
801 case CSR_SEPC
: return state
.sepc
& pc_alignment_mask();
802 case CSR_STVAL
: return state
.stval
;
803 case CSR_STVEC
: return state
.stvec
;
806 return state
.scause
| ((state
.scause
>> (max_xlen
-1)) << (xlen
-1));
809 if (get_field(state
.mstatus
, MSTATUS_TVM
))
810 require_privilege(PRV_M
);
812 case CSR_SSCRATCH
: return state
.sscratch
;
813 case CSR_MSTATUS
: return state
.mstatus
;
814 case CSR_MIP
: return state
.mip
;
815 case CSR_MIE
: return state
.mie
;
816 case CSR_MEPC
: return state
.mepc
& pc_alignment_mask();
817 case CSR_MSCRATCH
: return state
.mscratch
;
818 case CSR_MCAUSE
: return state
.mcause
;
819 case CSR_MTVAL
: return state
.mtval
;
820 case CSR_MISA
: return state
.misa
;
821 case CSR_MARCHID
: return 0;
822 case CSR_MIMPID
: return 0;
823 case CSR_MVENDORID
: return 0;
824 case CSR_MHARTID
: return id
;
825 case CSR_MTVEC
: return state
.mtvec
;
826 case CSR_MEDELEG
: return state
.medeleg
;
827 case CSR_MIDELEG
: return state
.mideleg
;
828 case CSR_TSELECT
: return state
.tselect
;
830 if (state
.tselect
< state
.num_triggers
) {
832 mcontrol_t
*mc
= &state
.mcontrol
[state
.tselect
];
833 v
= set_field(v
, MCONTROL_TYPE(xlen
), mc
->type
);
834 v
= set_field(v
, MCONTROL_DMODE(xlen
), mc
->dmode
);
835 v
= set_field(v
, MCONTROL_MASKMAX(xlen
), mc
->maskmax
);
836 v
= set_field(v
, MCONTROL_SELECT
, mc
->select
);
837 v
= set_field(v
, MCONTROL_TIMING
, mc
->timing
);
838 v
= set_field(v
, MCONTROL_ACTION
, mc
->action
);
839 v
= set_field(v
, MCONTROL_CHAIN
, mc
->chain
);
840 v
= set_field(v
, MCONTROL_MATCH
, mc
->match
);
841 v
= set_field(v
, MCONTROL_M
, mc
->m
);
842 v
= set_field(v
, MCONTROL_H
, mc
->h
);
843 v
= set_field(v
, MCONTROL_S
, mc
->s
);
844 v
= set_field(v
, MCONTROL_U
, mc
->u
);
845 v
= set_field(v
, MCONTROL_EXECUTE
, mc
->execute
);
846 v
= set_field(v
, MCONTROL_STORE
, mc
->store
);
847 v
= set_field(v
, MCONTROL_LOAD
, mc
->load
);
854 if (state
.tselect
< state
.num_triggers
) {
855 return state
.tdata2
[state
.tselect
];
860 case CSR_TDATA3
: return 0;
864 v
= set_field(v
, DCSR_XDEBUGVER
, 1);
865 v
= set_field(v
, DCSR_EBREAKM
, state
.dcsr
.ebreakm
);
866 v
= set_field(v
, DCSR_EBREAKH
, state
.dcsr
.ebreakh
);
867 v
= set_field(v
, DCSR_EBREAKS
, state
.dcsr
.ebreaks
);
868 v
= set_field(v
, DCSR_EBREAKU
, state
.dcsr
.ebreaku
);
869 v
= set_field(v
, DCSR_STOPCYCLE
, 0);
870 v
= set_field(v
, DCSR_STOPTIME
, 0);
871 v
= set_field(v
, DCSR_CAUSE
, state
.dcsr
.cause
);
872 v
= set_field(v
, DCSR_STEP
, state
.dcsr
.step
);
873 v
= set_field(v
, DCSR_PRV
, state
.dcsr
.prv
);
877 return state
.dpc
& pc_alignment_mask();
879 return state
.dscratch
;
881 throw trap_illegal_instruction(0);
884 reg_t
illegal_instruction(processor_t
* p
, insn_t insn
, reg_t pc
)
886 throw trap_illegal_instruction(0);
889 insn_func_t
processor_t::decode_insn(insn_t insn
)
891 // look up opcode in hash table
892 size_t idx
= insn
.bits() % OPCODE_CACHE_SIZE
;
893 insn_desc_t desc
= opcode_cache
[idx
];
895 if (unlikely(insn
.bits() != desc
.match
)) {
896 // fall back to linear search
897 insn_desc_t
* p
= &instructions
[0];
898 while ((insn
.bits() & p
->mask
) != p
->match
)
902 if (p
->mask
!= 0 && p
> &instructions
[0]) {
903 if (p
->match
!= (p
-1)->match
&& p
->match
!= (p
+1)->match
) {
904 // move to front of opcode list to reduce miss penalty
905 while (--p
>= &instructions
[0])
907 instructions
[0] = desc
;
911 opcode_cache
[idx
] = desc
;
912 opcode_cache
[idx
].match
= insn
.bits();
915 return xlen
== 64 ? desc
.rv64
: desc
.rv32
;
918 void processor_t::register_insn(insn_desc_t desc
)
920 instructions
.push_back(desc
);
923 void processor_t::build_opcode_map()
926 bool operator()(const insn_desc_t
& lhs
, const insn_desc_t
& rhs
) {
927 if (lhs
.match
== rhs
.match
)
928 return lhs
.mask
> rhs
.mask
;
929 return lhs
.match
> rhs
.match
;
932 std::sort(instructions
.begin(), instructions
.end(), cmp());
934 for (size_t i
= 0; i
< OPCODE_CACHE_SIZE
; i
++)
935 opcode_cache
[i
] = {0, 0, &illegal_instruction
, &illegal_instruction
};
938 void processor_t::register_extension(extension_t
* x
)
940 for (auto insn
: x
->get_instructions())
943 for (auto disasm_insn
: x
->get_disasms())
944 disassembler
->add_insn(disasm_insn
);
946 throw std::logic_error("only one extension may be registered");
948 x
->set_processor(this);
951 void processor_t::register_base_instructions()
953 #define DECLARE_INSN(name, match, mask) \
954 insn_bits_t name##_match = (match), name##_mask = (mask);
955 #include "encoding.h"
958 #define DEFINE_INSN(name) \
959 REGISTER_INSN(this, name, name##_match, name##_mask)
960 #include "insn_list.h"
963 register_insn({0, 0, &illegal_instruction
, &illegal_instruction
});
967 bool processor_t::load(reg_t addr
, size_t len
, uint8_t* bytes
)
973 memset(bytes
, 0, len
);
974 bytes
[0] = get_field(state
.mip
, MIP_MSIP
);
983 bool processor_t::store(reg_t addr
, size_t len
, const uint8_t* bytes
)
989 state
.mip
= set_field(state
.mip
, MIP_MSIP
, bytes
[0]);
998 void processor_t::trigger_updated()
1001 mmu
->check_triggers_fetch
= false;
1002 mmu
->check_triggers_load
= false;
1003 mmu
->check_triggers_store
= false;
1005 for (unsigned i
= 0; i
< state
.num_triggers
; i
++) {
1006 if (state
.mcontrol
[i
].execute
) {
1007 mmu
->check_triggers_fetch
= true;
1009 if (state
.mcontrol
[i
].load
) {
1010 mmu
->check_triggers_load
= true;
1012 if (state
.mcontrol
[i
].store
) {
1013 mmu
->check_triggers_store
= true;