riscv/processor.cc

   1 // See LICENSE for license details.
   2
   3 #include "processor.h"
   4 #include "extension.h"
   5 #include "common.h"
   6 #include "config.h"
   7 #include "simif.h"
   8 #include "mmu.h"
   9 #include "disasm.h"
  10 #include <cinttypes>
  11 #include <cmath>
  12 #include <cstdlib>
  13 #include <iostream>
  14 #include <assert.h>
  15 #include <limits.h>
  16 #include <stdexcept>
  17 #include <algorithm>
  18 #ifdef SPIKE_SIMPLEV
  19 #include "sv_insn_redirect.h"
  20 #endif
  21
  22 #undef STATE
  23 #define STATE state
  24
  25 processor_t::processor_t(const char* isa, simif_t* sim, uint32_t id,
  26         bool halt_on_reset)
  27   : debug(false), halt_request(false), sim(sim), ext(NULL), id(id),
  28   halt_on_reset(halt_on_reset), last_pc(1), executions(1)
  29 #ifdef SPIKE_SIMPLEV
  30     , s(this)
  31 #endif
  32 {
  33   parse_isa_string(isa);
  34   register_base_instructions();
  35
  36 #ifdef SPIKE_SIMPLEV
  37   mmu = new sv_mmu_t(sim, this);
  38 #else
  39   mmu = new mmu_t(sim, this);
  40 #endif
  41
  42   disassembler = new disassembler_t(max_xlen);
  43   if (ext)
  44     for (auto disasm_insn : ext->get_disasms())
  45       disassembler->add_insn(disasm_insn);
  46
  47   reset();
  48 }
  49
  50 processor_t::~processor_t()
  51 {
  52 #ifdef RISCV_ENABLE_HISTOGRAM
  53   if (histogram_enabled)
  54   {
  55     fprintf(stderr, "PC Histogram size:%zu\n", pc_histogram.size());
  56     for (auto it : pc_histogram)
  57       fprintf(stderr, "%0" PRIx64 " %" PRIu64 "\n", it.first, it.second);
  58   }
  59 #endif
  60
  61   delete mmu;
  62   delete disassembler;
  63 }
  64
  65 static void bad_isa_string(const char* isa)
  66 {
  67   fprintf(stderr, "error: bad --isa option %s\n", isa);
  68   abort();
  69 }
  70
  71 void processor_t::parse_isa_string(const char* str)
  72 {
  73   std::string lowercase, tmp;
  74   for (const char *r = str; *r; r++)
  75     lowercase += std::tolower(*r);
  76
  77   const char* p = lowercase.c_str();
  78   const char* all_subsets = "imafdqc";
  79
  80   max_xlen = 64;
  81   state.misa = reg_t(2) << 62;
  82
  83   if (strncmp(p, "rv32", 4) == 0)
  84     max_xlen = 32, state.misa = reg_t(1) << 30, p += 4;
  85   else if (strncmp(p, "rv64", 4) == 0)
  86     p += 4;
  87   else if (strncmp(p, "rv", 2) == 0)
  88     p += 2;
  89
  90   if (!*p) {
  91     p = "imafdc";
  92   } else if (*p == 'g') { // treat "G" as "IMAFD"
  93     tmp = std::string("imafd") + (p+1);
  94     p = &tmp[0];
  95   } else if (*p != 'i') {
  96     bad_isa_string(str);
  97   }
  98
  99   isa_string = "rv" + std::to_string(max_xlen) + p;
 100   state.misa |= 1L << ('s' - 'a'); // advertise support for supervisor mode
 101   state.misa |= 1L << ('u' - 'a'); // advertise support for user mode
 102
 103   while (*p) {
 104     state.misa |= 1L << (*p - 'a');
 105
 106     if (auto next = strchr(all_subsets, *p)) {
 107       all_subsets = next + 1;
 108       p++;
 109     } else if (*p == 'x') {
 110       const char* ext = p+1, *end = ext;
 111       while (islower(*end))
 112         end++;
 113       register_extension(find_extension(std::string(ext, end - ext).c_str())());
 114       p = end;
 115     } else {
 116       bad_isa_string(str);
 117     }
 118   }
 119
 120   if (supports_extension('D') && !supports_extension('F'))
 121     bad_isa_string(str);
 122
 123   if (supports_extension('Q') && !supports_extension('D'))
 124     bad_isa_string(str);
 125
 126   if (supports_extension('Q') && max_xlen < 64)
 127     bad_isa_string(str);
 128
 129   max_isa = state.misa;
 130 }
 131
 132 void state_t::reset(reg_t max_isa)
 133 {
 134   memset(this, 0, sizeof(*this));
 135   misa = max_isa;
 136   prv = PRV_M;
 137   pc = DEFAULT_RSTVEC;
 138   tselect = 0;
 139   for (unsigned int i = 0; i < num_triggers; i++)
 140     mcontrol[i].type = 2;
 141 }
 142
 143 void processor_t::set_debug(bool value)
 144 {
 145   debug = value;
 146   if (ext)
 147     ext->set_debug(value);
 148 }
 149
 150 void processor_t::set_histogram(bool value)
 151 {
 152   histogram_enabled = value;
 153 #ifndef RISCV_ENABLE_HISTOGRAM
 154   if (value) {
 155     fprintf(stderr, "PC Histogram support has not been properly enabled;");
 156     fprintf(stderr, " please re-build the riscv-isa-run project using \"configure --enable-histogram\".\n");
 157   }
 158 #endif
 159 }
 160
 161 void processor_t::reset()
 162 {
 163   state.reset(max_isa);
 164   state.dcsr.halt = halt_on_reset;
 165   halt_on_reset = false;
 166   set_csr(CSR_MSTATUS, state.mstatus);
 167
 168   if (ext)
 169     ext->reset(); // reset the extension
 170
 171   if (sim)
 172     sim->proc_reset(id);
 173 }
 174
 175 // Count number of contiguous 0 bits starting from the LSB.
 176 static int ctz(reg_t val)
 177 {
 178   int res = 0;
 179   if (val)
 180     while ((val & 1) == 0)
 181       val >>= 1, res++;
 182   return res;
 183 }
 184
 185 void processor_t::take_interrupt(reg_t pending_interrupts)
 186 {
 187   reg_t mie = get_field(state.mstatus, MSTATUS_MIE);
 188   reg_t m_enabled = state.prv < PRV_M || (state.prv == PRV_M && mie);
 189   reg_t enabled_interrupts = pending_interrupts & ~state.mideleg & -m_enabled;
 190
 191   reg_t sie = get_field(state.mstatus, MSTATUS_SIE);
 192   reg_t s_enabled = state.prv < PRV_S || (state.prv == PRV_S && sie);
 193   // M-ints have highest priority; consider S-ints only if no M-ints pending
 194   if (enabled_interrupts == 0)
 195     enabled_interrupts = pending_interrupts & state.mideleg & -s_enabled;
 196
 197   if (state.dcsr.cause == 0 && enabled_interrupts) {
 198     // nonstandard interrupts have highest priority
 199     if (enabled_interrupts >> IRQ_M_EXT)
 200       enabled_interrupts = enabled_interrupts >> IRQ_M_EXT << IRQ_M_EXT;
 201     // external interrupts have next-highest priority
 202     else if (enabled_interrupts & (MIP_MEIP | MIP_SEIP))
 203       enabled_interrupts = enabled_interrupts & (MIP_MEIP | MIP_SEIP);
 204     // software interrupts have next-highest priority
 205     else if (enabled_interrupts & (MIP_MSIP | MIP_SSIP))
 206       enabled_interrupts = enabled_interrupts & (MIP_MSIP | MIP_SSIP);
 207     // timer interrupts have next-highest priority
 208     else if (enabled_interrupts & (MIP_MTIP | MIP_STIP))
 209       enabled_interrupts = enabled_interrupts & (MIP_MTIP | MIP_STIP);
 210     else
 211       abort();
 212
 213     throw trap_t(((reg_t)1 << (max_xlen-1)) | ctz(enabled_interrupts));
 214   }
 215 }
 216
 217 static int xlen_to_uxl(int xlen)
 218 {
 219   if (xlen == 32)
 220     return 1;
 221   if (xlen == 64)
 222     return 2;
 223   abort();
 224 }
 225
 226 reg_t processor_t::legalize_privilege(reg_t prv)
 227 {
 228   assert(prv <= PRV_M);
 229
 230   if (!supports_extension('U'))
 231     return PRV_M;
 232
 233   if (prv == PRV_H || !supports_extension('S'))
 234     return PRV_U;
 235
 236   return prv;
 237 }
 238
 239 void processor_t::set_privilege(reg_t prv)
 240 {
 241   mmu->flush_tlb();
 242   state.prv = legalize_privilege(prv);
 243 }
 244
 245 void processor_t::enter_debug_mode(uint8_t cause)
 246 {
 247   state.dcsr.cause = cause;
 248   state.dcsr.prv = state.prv;
 249   set_privilege(PRV_M);
 250   state.dpc = state.pc;
 251   state.pc = DEBUG_ROM_ENTRY;
 252 }
 253
 254 void processor_t::take_trap(trap_t& t, reg_t epc)
 255 {
 256   if (debug) {
 257     fprintf(stderr, "core %3d: exception %s, epc 0x%016" PRIx64 "\n",
 258             id, t.name(), epc);
 259     if (t.has_tval())
 260       fprintf(stderr, "core %3d:           tval 0x%016" PRIx64 "\n", id,
 261           t.get_tval());
 262   }
 263
 264   if (state.dcsr.cause) {
 265     if (t.cause() == CAUSE_BREAKPOINT) {
 266       state.pc = DEBUG_ROM_ENTRY;
 267     } else {
 268       state.pc = DEBUG_ROM_TVEC;
 269     }
 270     return;
 271   }
 272
 273   if (t.cause() == CAUSE_BREAKPOINT && (
 274               (state.prv == PRV_M && state.dcsr.ebreakm) ||
 275               (state.prv == PRV_S && state.dcsr.ebreaks) ||
 276               (state.prv == PRV_U && state.dcsr.ebreaku))) {
 277     enter_debug_mode(DCSR_CAUSE_SWBP);
 278     return;
 279   }
 280
 281   // by default, trap to M-mode, unless delegated to S-mode
 282   reg_t bit = t.cause();
 283   reg_t deleg = state.medeleg;
 284   bool interrupt = (bit & ((reg_t)1 << (max_xlen-1))) != 0;
 285   if (interrupt)
 286     deleg = state.mideleg, bit &= ~((reg_t)1 << (max_xlen-1));
 287   if (state.prv <= PRV_S && bit < max_xlen && ((deleg >> bit) & 1)) {
 288     // handle the trap in S-mode
 289     state.pc = state.stvec;
 290     state.scause = t.cause();
 291     state.sepc = epc;
 292     state.stval = t.get_tval();
 293
 294     reg_t s = state.mstatus;
 295     s = set_field(s, MSTATUS_SPIE, get_field(s, MSTATUS_SIE));
 296     s = set_field(s, MSTATUS_SPP, state.prv);
 297     s = set_field(s, MSTATUS_SIE, 0);
 298     set_csr(CSR_MSTATUS, s);
 299     set_privilege(PRV_S);
 300   } else {
 301     reg_t vector = (state.mtvec & 1) && interrupt ? 4*bit : 0;
 302     state.pc = (state.mtvec & ~(reg_t)1) + vector;
 303     state.mepc = epc;
 304     state.mcause = t.cause();
 305     state.mtval = t.get_tval();
 306
 307     reg_t s = state.mstatus;
 308     s = set_field(s, MSTATUS_MPIE, get_field(s, MSTATUS_MIE));
 309     s = set_field(s, MSTATUS_MPP, state.prv);
 310     s = set_field(s, MSTATUS_MIE, 0);
 311     set_csr(CSR_MSTATUS, s);
 312     set_privilege(PRV_M);
 313   }
 314 }
 315
 316 void processor_t::disasm(insn_t insn)
 317 {
 318   uint64_t bits = insn.bits() & ((1ULL << (8 * insn_length(insn.bits()))) - 1);
 319   if (last_pc != state.pc || last_bits != bits) {
 320     if (executions != 1) {
 321       fprintf(stderr, "core %3d: Executed %" PRIx64 " times\n", id, executions);
 322     }
 323
 324     fprintf(stderr, "core %3d: 0x%016" PRIx64 " (0x%08" PRIx64 ") %s\n",
 325             id, state.pc, bits, disassembler->disassemble(insn).c_str());
 326     last_pc = state.pc;
 327     last_bits = bits;
 328     executions = 1;
 329   } else {
 330     executions++;
 331   }
 332 }
 333
 334 int processor_t::paddr_bits()
 335 {
 336   assert(xlen == max_xlen);
 337   return max_xlen == 64 ? 50 : 34;
 338 }
 339
 340 void processor_t::set_csr(int which, reg_t val)
 341 {
 342   val = _zext_xlen(val);
 343   reg_t delegable_ints = MIP_SSIP | MIP_STIP | MIP_SEIP
 344                        | ((ext != NULL) << IRQ_COP);
 345   reg_t all_ints = delegable_ints | MIP_MSIP | MIP_MTIP;
 346   fprintf(stderr, "set CSR %x %lx\n", which, val);
 347   switch (which)
 348   {
 349 #ifdef SPIKE_SIMPLEV
 350     case CSR_USVMVL:
 351       state.mvl = std::min(val, (uint64_t)64); // limited to XLEN width
 352       // TODO XXX throw exception if val == 0
 353       fprintf(stderr, "set MVL %lx\n", state.mvl);
 354       break;
 355     case CSR_USVSTATE:
 356       // bits 0-5: mvl - 6-11: vl - 12-17: srcoffs - 18-23: destoffs
 357       set_csr(CSR_USVMVL, get_field(val, 0x1f   )+1);
 358       set_csr(CSR_USVVL , get_field(val, 0x1f<<6)+1);
 359       state.srcoffs  = std::min(get_field(val, 0x1f<<12), state.vl-1);
 360       state.destoffs = std::min(get_field(val, 0x1f<<18), state.vl-1);
 361       break;
 362     case CSR_USVVL:
 363       state.vl = std::min(state.mvl, val);
 364       // TODO XXX throw exception if val == 0
 365       fprintf(stderr, "set VL %lx\n", state.vl);
 366       break;
 367     case CSR_SVREGCFG0:
 368     case CSR_SVREGCFG1:
 369     case CSR_SVREGCFG2:
 370     case CSR_SVREGCFG3:
 371     case CSR_SVREGCFG4:
 372     case CSR_SVREGCFG5:
 373     case CSR_SVREGCFG6:
 374     case CSR_SVREGCFG7:
 375     {
 376       // identify which (pair) of SV config CAM registers are being set
 377       int tbidx = (which - CSR_SVREGCFG0) * 2;
 378       fprintf(stderr, "set REGCFG %d %lx\n", tbidx, val);
 379       // lower 16 bits go into even, upper into odd...
 380       state.sv_csrs[tbidx].u = get_field(val, 0xffff);
 381       state.sv_csrs[tbidx+1].u = get_field(val, 0xffff<<16);
 382       int clroffset = 2;
 383       if (xlen == 64)
 384       {
 385           state.sv_csrs[tbidx+2].u = get_field(val, 0xffffUL<<32);
 386           state.sv_csrs[tbidx+3].u = get_field(val, 0xffffUL<<48);
 387         clroffset = 4;
 388       }
 389       // clear out all CSRs above the one(s) being set: this ensures that
 390       // when it comes to context-switching, it's clear what needs to be saved
 391       for (int i = tbidx+clroffset; i < 16; i++)
 392       {
 393           fprintf(stderr, "clr REGCFG %d\n", i);
 394           state.sv_csrs[i].u = 0;
 395       }
 396       // okaaay and now "unpack" the CAM to make it easier to use.  this
 397       // approach is not designed to be efficient right now.  optimise later
 398       // first clear the old tables
 399       memset(state.sv_int_tb, 0, sizeof(state.sv_int_tb));
 400       memset(state.sv_fp_tb, 0, sizeof(state.sv_fp_tb));
 401       // now walk the CAM and unpack it
 402       for (int i = 0; i < SV_CSR_SZ; i++)
 403       {
 404         union sv_reg_csr_entry *c = &state.sv_csrs[i];
 405         uint64_t idx = c->b.regkey;
 406         sv_reg_entry *r;
 407         if (c->u == 0)
 408         {
 409             break;
 410         }
 411         // XXX damn.  this basically duplicates sv_insn_t::get_regentry.
 412         if (c->b.type == 1)
 413         {
 414             r = &state.sv_int_tb[idx];
 415         }
 416         else
 417         {
 418             r = &state.sv_fp_tb[idx];
 419         }
 420         r->elwidth = c->b.elwidth;
 421         r->regidx = c->b.regidx;
 422         r->isvec = c->b.isvec;
 423         r->active = true;
 424         fprintf(stderr, "setting REGCFG type:%d isvec:%d %d %d\n",
 425                         c->b.type, r->isvec, (int)idx, (int)r->regidx);
 426       }
 427       break;
 428     }
 429     case CSR_SVPREDCFG0:
 430     case CSR_SVPREDCFG1:
 431     case CSR_SVPREDCFG2:
 432     case CSR_SVPREDCFG3:
 433     case CSR_SVPREDCFG4:
 434     case CSR_SVPREDCFG5:
 435     case CSR_SVPREDCFG6:
 436     case CSR_SVPREDCFG7:
 437     {
 438       // comments removed as it's near-identical to the regs version
 439       // TODO: macro-ify
 440       int tbidx = (which - CSR_SVPREDCFG0) * 2;
 441       state.sv_pred_csrs[tbidx].u = get_field(val, 0xffff);
 442       state.sv_pred_csrs[tbidx+1].u = get_field(val, 0xffff0000);
 443       int clroffset = 2;
 444       if (xlen == 64)
 445       {
 446           state.sv_pred_csrs[tbidx+2].u = get_field(val, 0xffffUL<<32);
 447           state.sv_pred_csrs[tbidx+3].u = get_field(val, 0xffffUL<<48);
 448           clroffset = 4;
 449       }
 450       for (int i = tbidx+clroffset; i < 16; i++)
 451       {
 452           state.sv_pred_csrs[i].u = 0;
 453       }
 454       memset(state.sv_pred_int_tb, 0, sizeof(state.sv_pred_int_tb));
 455       memset(state.sv_pred_fp_tb, 0, sizeof(state.sv_pred_fp_tb));
 456       for (int i = 0; i < SV_CSR_SZ; i++)
 457       {
 458         union sv_pred_csr_entry *c = &state.sv_pred_csrs[i];
 459         uint64_t idx = c->b.regkey;
 460         if (c->u == 0)
 461         {
 462             break;
 463         }
 464         sv_pred_entry *r;
 465         // XXX damn.  this basically duplicates sv_insn_t::get_predentry.
 466         if (c->b.type == 1)
 467         {
 468             r = &state.sv_pred_int_tb[idx];
 469         }
 470         else
 471         {
 472             r = &state.sv_pred_fp_tb[idx];
 473         }
 474         r->regidx = c->b.regidx;
 475         r->zero   = c->b.zero;
 476         r->inv    = c->b.inv;
 477         r->packed = c->b.packed;
 478         r->active = true;
 479         fprintf(stderr, "setting PREDCFG type:%d zero:%d %d %d\n",
 480                         c->b.type, r->zero, (int)idx, (int)r->regidx);
 481       }
 482       break;
 483     }
 484 #endif
 485     case CSR_FFLAGS:
 486       dirty_fp_state;
 487       state.fflags = val & (FSR_AEXC >> FSR_AEXC_SHIFT);
 488       break;
 489     case CSR_FRM:
 490       dirty_fp_state;
 491       state.frm = val & (FSR_RD >> FSR_RD_SHIFT);
 492       break;
 493     case CSR_FCSR:
 494       dirty_fp_state;
 495       state.fflags = (val & FSR_AEXC) >> FSR_AEXC_SHIFT;
 496       state.frm = (val & FSR_RD) >> FSR_RD_SHIFT;
 497       break;
 498     case CSR_MSTATUS: {
 499       if ((val ^ state.mstatus) &
 500           (MSTATUS_MPP | MSTATUS_MPRV | MSTATUS_SUM | MSTATUS_MXR))
 501         mmu->flush_tlb();
 502
 503       reg_t mask = MSTATUS_SIE | MSTATUS_SPIE | MSTATUS_MIE | MSTATUS_MPIE
 504                  | MSTATUS_FS | MSTATUS_MPRV | MSTATUS_SUM
 505                  | MSTATUS_MXR | MSTATUS_TW | MSTATUS_TVM
 506                  | MSTATUS_TSR | MSTATUS_UXL | MSTATUS_SXL |
 507                  (ext ? MSTATUS_XS : 0);
 508
 509       reg_t requested_mpp = legalize_privilege(get_field(val, MSTATUS_MPP));
 510       state.mstatus = set_field(state.mstatus, MSTATUS_MPP, requested_mpp);
 511       if (supports_extension('S'))
 512         mask |= MSTATUS_SPP;
 513
 514       state.mstatus = (state.mstatus & ~mask) | (val & mask);
 515
 516       bool dirty = (state.mstatus & MSTATUS_FS) == MSTATUS_FS;
 517       dirty |= (state.mstatus & MSTATUS_XS) == MSTATUS_XS;
 518       if (max_xlen == 32)
 519         state.mstatus = set_field(state.mstatus, MSTATUS32_SD, dirty);
 520       else
 521         state.mstatus = set_field(state.mstatus, MSTATUS64_SD, dirty);
 522
 523       state.mstatus = set_field(state.mstatus, MSTATUS_UXL, xlen_to_uxl(max_xlen));
 524       state.mstatus = set_field(state.mstatus, MSTATUS_UXL, xlen_to_uxl(max_xlen));
 525       state.mstatus = set_field(state.mstatus, MSTATUS_SXL, xlen_to_uxl(max_xlen));
 526       // U-XLEN == S-XLEN == M-XLEN
 527       xlen = max_xlen;
 528       break;
 529     }
 530     case CSR_MIP: {
 531       reg_t mask = MIP_SSIP | MIP_STIP;
 532       state.mip = (state.mip & ~mask) | (val & mask);
 533       break;
 534     }
 535     case CSR_MIE:
 536       state.mie = (state.mie & ~all_ints) | (val & all_ints);
 537       break;
 538     case CSR_MIDELEG:
 539       state.mideleg = (state.mideleg & ~delegable_ints) | (val & delegable_ints);
 540       break;
 541     case CSR_MEDELEG: {
 542       reg_t mask =
 543         (1 << CAUSE_MISALIGNED_FETCH) |
 544         (1 << CAUSE_BREAKPOINT) |
 545         (1 << CAUSE_USER_ECALL) |
 546         (1 << CAUSE_FETCH_PAGE_FAULT) |
 547         (1 << CAUSE_LOAD_PAGE_FAULT) |
 548         (1 << CAUSE_STORE_PAGE_FAULT);
 549       state.medeleg = (state.medeleg & ~mask) | (val & mask);
 550       break;
 551     }
 552     case CSR_MINSTRET:
 553     case CSR_MCYCLE:
 554       if (xlen == 32)
 555         state.minstret = (state.minstret >> 32 << 32) | (val & 0xffffffffU);
 556       else
 557         state.minstret = val;
 558       // The ISA mandates that if an instruction writes instret, the write
 559       // takes precedence over the increment to instret.  However, Spike
 560       // unconditionally increments instret after executing an instruction.
 561       // Correct for this artifact by decrementing instret here.
 562       state.minstret--;
 563       break;
 564     case CSR_MINSTRETH:
 565     case CSR_MCYCLEH:
 566       state.minstret = (val << 32) | (state.minstret << 32 >> 32);
 567       state.minstret--; // See comment above.
 568       break;
 569     case CSR_SCOUNTEREN:
 570       state.scounteren = val;
 571       break;
 572     case CSR_MCOUNTEREN:
 573       state.mcounteren = val;
 574       break;
 575     case CSR_SSTATUS: {
 576       reg_t mask = SSTATUS_SIE | SSTATUS_SPIE | SSTATUS_SPP | SSTATUS_FS
 577                  | SSTATUS_XS | SSTATUS_SUM | SSTATUS_MXR;
 578       return set_csr(CSR_MSTATUS, (state.mstatus & ~mask) | (val & mask));
 579     }
 580     case CSR_SIP: {
 581       reg_t mask = MIP_SSIP & state.mideleg;
 582       return set_csr(CSR_MIP, (state.mip & ~mask) | (val & mask));
 583     }
 584     case CSR_SIE:
 585       return set_csr(CSR_MIE,
 586                      (state.mie & ~state.mideleg) | (val & state.mideleg));
 587     case CSR_SATP: {
 588       mmu->flush_tlb();
 589       if (max_xlen == 32)
 590         state.satp = val & (SATP32_PPN | SATP32_MODE);
 591       if (max_xlen == 64 && (get_field(val, SATP64_MODE) == SATP_MODE_OFF ||
 592                              get_field(val, SATP64_MODE) == SATP_MODE_SV39 ||
 593                              get_field(val, SATP64_MODE) == SATP_MODE_SV48))
 594         state.satp = val & (SATP64_PPN | SATP64_MODE);
 595       break;
 596     }
 597     case CSR_SEPC: state.sepc = val & ~(reg_t)1; break;
 598     case CSR_STVEC: state.stvec = val >> 2 << 2; break;
 599     case CSR_SSCRATCH: state.sscratch = val; break;
 600     case CSR_SCAUSE: state.scause = val; break;
 601     case CSR_STVAL: state.stval = val; break;
 602     case CSR_MEPC: state.mepc = val & ~(reg_t)1; break;
 603     case CSR_MTVEC: state.mtvec = val & ~(reg_t)2; break;
 604     case CSR_MSCRATCH: state.mscratch = val; break;
 605     case CSR_MCAUSE: state.mcause = val; break;
 606     case CSR_MTVAL: state.mtval = val; break;
 607     case CSR_MISA: {
 608       // the write is ignored if increasing IALIGN would misalign the PC
 609       if (!(val & (1L << ('C' - 'A'))) && (state.pc & 2))
 610         break;
 611
 612       if (!(val & (1L << ('F' - 'A'))))
 613         val &= ~(1L << ('D' - 'A'));
 614
 615       // allow MAFDC bits in MISA to be modified
 616       reg_t mask = 0;
 617       mask |= 1L << ('M' - 'A');
 618       mask |= 1L << ('A' - 'A');
 619       mask |= 1L << ('F' - 'A');
 620       mask |= 1L << ('D' - 'A');
 621       mask |= 1L << ('C' - 'A');
 622       mask &= max_isa;
 623
 624       state.misa = (val & mask) | (state.misa & ~mask);
 625       break;
 626     }
 627     case CSR_TSELECT:
 628       if (val < state.num_triggers) {
 629         state.tselect = val;
 630       }
 631       break;
 632     case CSR_TDATA1:
 633       {
 634         mcontrol_t *mc = &state.mcontrol[state.tselect];
 635         if (mc->dmode && !state.dcsr.cause) {
 636           break;
 637         }
 638         mc->dmode = get_field(val, MCONTROL_DMODE(xlen));
 639         mc->select = get_field(val, MCONTROL_SELECT);
 640         mc->timing = get_field(val, MCONTROL_TIMING);
 641         mc->action = (mcontrol_action_t) get_field(val, MCONTROL_ACTION);
 642         mc->chain = get_field(val, MCONTROL_CHAIN);
 643         mc->match = (mcontrol_match_t) get_field(val, MCONTROL_MATCH);
 644         mc->m = get_field(val, MCONTROL_M);
 645         mc->h = get_field(val, MCONTROL_H);
 646         mc->s = get_field(val, MCONTROL_S);
 647         mc->u = get_field(val, MCONTROL_U);
 648         mc->execute = get_field(val, MCONTROL_EXECUTE);
 649         mc->store = get_field(val, MCONTROL_STORE);
 650         mc->load = get_field(val, MCONTROL_LOAD);
 651         // Assume we're here because of csrw.
 652         if (mc->execute)
 653           mc->timing = 0;
 654         trigger_updated();
 655       }
 656       break;
 657     case CSR_TDATA2:
 658       if (state.mcontrol[state.tselect].dmode && !state.dcsr.cause) {
 659         break;
 660       }
 661       if (state.tselect < state.num_triggers) {
 662         state.tdata2[state.tselect] = val;
 663       }
 664       break;
 665     case CSR_DCSR:
 666       state.dcsr.prv = get_field(val, DCSR_PRV);
 667       state.dcsr.step = get_field(val, DCSR_STEP);
 668       // TODO: ndreset and fullreset
 669       state.dcsr.ebreakm = get_field(val, DCSR_EBREAKM);
 670       state.dcsr.ebreakh = get_field(val, DCSR_EBREAKH);
 671       state.dcsr.ebreaks = get_field(val, DCSR_EBREAKS);
 672       state.dcsr.ebreaku = get_field(val, DCSR_EBREAKU);
 673       state.dcsr.halt = get_field(val, DCSR_HALT);
 674       break;
 675     case CSR_DPC:
 676       state.dpc = val & ~(reg_t)1;
 677       break;
 678     case CSR_DSCRATCH:
 679       state.dscratch = val;
 680       break;
 681   }
 682 }
 683
 684 reg_t processor_t::get_csr(int which)
 685 {
 686   uint32_t ctr_en = -1;
 687   if (state.prv < PRV_M)
 688     ctr_en &= state.mcounteren;
 689   if (state.prv < PRV_S)
 690     ctr_en &= state.scounteren;
 691   bool ctr_ok = (ctr_en >> (which & 31)) & 1;
 692
 693   if (ctr_ok) {
 694     if (which >= CSR_HPMCOUNTER3 && which <= CSR_HPMCOUNTER31)
 695       return 0;
 696     if (xlen == 32 && which >= CSR_HPMCOUNTER3H && which <= CSR_HPMCOUNTER31H)
 697       return 0;
 698   }
 699   if (which >= CSR_MHPMCOUNTER3 && which <= CSR_MHPMCOUNTER31)
 700     return 0;
 701   if (xlen == 32 && which >= CSR_MHPMCOUNTER3H && which <= CSR_MHPMCOUNTER31H)
 702     return 0;
 703   if (which >= CSR_MHPMEVENT3 && which <= CSR_MHPMEVENT31)
 704     return 0;
 705
 706   switch (which)
 707   {
 708 #ifdef SPIKE_SIMPLEV
 709     case CSR_USVVL:
 710       return state.vl;
 711     case CSR_USVSTATE:
 712       return (state.vl-1)            | ((state.mvl-1)<<6) |
 713              (state.srcoffs<<12)     | (state.destoffs<<18) ;
 714     case CSR_USVMVL:
 715       return state.mvl;
 716     case CSR_SVREGCFG0:
 717     case CSR_SVREGCFG1:
 718     case CSR_SVREGCFG2:
 719     case CSR_SVREGCFG3:
 720     case CSR_SVREGCFG4:
 721     case CSR_SVREGCFG5:
 722     case CSR_SVREGCFG6:
 723     case CSR_SVREGCFG7:
 724       return 0;// XXX TODO: return correct entry
 725     case CSR_SVPREDCFG0:
 726     case CSR_SVPREDCFG1:
 727     case CSR_SVPREDCFG2:
 728     case CSR_SVPREDCFG3:
 729     case CSR_SVPREDCFG4:
 730     case CSR_SVPREDCFG5:
 731     case CSR_SVPREDCFG6:
 732     case CSR_SVPREDCFG7:
 733       return 0;// XXX TODO: return correct entry
 734 #endif
 735     case CSR_FFLAGS:
 736       require_fp;
 737       if (!supports_extension('F'))
 738         break;
 739       return state.fflags;
 740     case CSR_FRM:
 741       require_fp;
 742       if (!supports_extension('F'))
 743         break;
 744       return state.frm;
 745     case CSR_FCSR:
 746       require_fp;
 747       if (!supports_extension('F'))
 748         break;
 749       return (state.fflags << FSR_AEXC_SHIFT) | (state.frm << FSR_RD_SHIFT);
 750     case CSR_INSTRET:
 751     case CSR_CYCLE:
 752       if (ctr_ok)
 753         return state.minstret;
 754       break;
 755     case CSR_MINSTRET:
 756     case CSR_MCYCLE:
 757       return state.minstret;
 758     case CSR_INSTRETH:
 759     case CSR_CYCLEH:
 760       if (ctr_ok && xlen == 32)
 761         return state.minstret >> 32;
 762       break;
 763     case CSR_MINSTRETH:
 764     case CSR_MCYCLEH:
 765       if (xlen == 32)
 766         return state.minstret >> 32;
 767       break;
 768     case CSR_SCOUNTEREN: return state.scounteren;
 769     case CSR_MCOUNTEREN: return state.mcounteren;
 770     case CSR_SSTATUS: {
 771       reg_t mask = SSTATUS_SIE | SSTATUS_SPIE | SSTATUS_SPP | SSTATUS_FS
 772                  | SSTATUS_XS | SSTATUS_SUM | SSTATUS_MXR | SSTATUS_UXL;
 773       reg_t sstatus = state.mstatus & mask;
 774       if ((sstatus & SSTATUS_FS) == SSTATUS_FS ||
 775           (sstatus & SSTATUS_XS) == SSTATUS_XS)
 776         sstatus |= (xlen == 32 ? SSTATUS32_SD : SSTATUS64_SD);
 777       return sstatus;
 778     }
 779     case CSR_SIP: return state.mip & state.mideleg;
 780     case CSR_SIE: return state.mie & state.mideleg;
 781     case CSR_SEPC: return state.sepc & pc_alignment_mask();
 782     case CSR_STVAL: return state.stval;
 783     case CSR_STVEC: return state.stvec;
 784     case CSR_SCAUSE:
 785       if (max_xlen > xlen)
 786         return state.scause | ((state.scause >> (max_xlen-1)) << (xlen-1));
 787       return state.scause;
 788     case CSR_SATP:
 789       if (get_field(state.mstatus, MSTATUS_TVM))
 790         require_privilege(PRV_M);
 791       return state.satp;
 792     case CSR_SSCRATCH: return state.sscratch;
 793     case CSR_MSTATUS: return state.mstatus;
 794     case CSR_MIP: return state.mip;
 795     case CSR_MIE: return state.mie;
 796     case CSR_MEPC: return state.mepc & pc_alignment_mask();
 797     case CSR_MSCRATCH: return state.mscratch;
 798     case CSR_MCAUSE: return state.mcause;
 799     case CSR_MTVAL: return state.mtval;
 800     case CSR_MISA: return state.misa;
 801     case CSR_MARCHID: return 0;
 802     case CSR_MIMPID: return 0;
 803     case CSR_MVENDORID: return 0;
 804     case CSR_MHARTID: return id;
 805     case CSR_MTVEC: return state.mtvec;
 806     case CSR_MEDELEG: return state.medeleg;
 807     case CSR_MIDELEG: return state.mideleg;
 808     case CSR_TSELECT: return state.tselect;
 809     case CSR_TDATA1:
 810       if (state.tselect < state.num_triggers) {
 811         reg_t v = 0;
 812         mcontrol_t *mc = &state.mcontrol[state.tselect];
 813         v = set_field(v, MCONTROL_TYPE(xlen), mc->type);
 814         v = set_field(v, MCONTROL_DMODE(xlen), mc->dmode);
 815         v = set_field(v, MCONTROL_MASKMAX(xlen), mc->maskmax);
 816         v = set_field(v, MCONTROL_SELECT, mc->select);
 817         v = set_field(v, MCONTROL_TIMING, mc->timing);
 818         v = set_field(v, MCONTROL_ACTION, mc->action);
 819         v = set_field(v, MCONTROL_CHAIN, mc->chain);
 820         v = set_field(v, MCONTROL_MATCH, mc->match);
 821         v = set_field(v, MCONTROL_M, mc->m);
 822         v = set_field(v, MCONTROL_H, mc->h);
 823         v = set_field(v, MCONTROL_S, mc->s);
 824         v = set_field(v, MCONTROL_U, mc->u);
 825         v = set_field(v, MCONTROL_EXECUTE, mc->execute);
 826         v = set_field(v, MCONTROL_STORE, mc->store);
 827         v = set_field(v, MCONTROL_LOAD, mc->load);
 828         return v;
 829       } else {
 830         return 0;
 831       }
 832       break;
 833     case CSR_TDATA2:
 834       if (state.tselect < state.num_triggers) {
 835         return state.tdata2[state.tselect];
 836       } else {
 837         return 0;
 838       }
 839       break;
 840     case CSR_TDATA3: return 0;
 841     case CSR_DCSR:
 842       {
 843         uint32_t v = 0;
 844         v = set_field(v, DCSR_XDEBUGVER, 1);
 845         v = set_field(v, DCSR_EBREAKM, state.dcsr.ebreakm);
 846         v = set_field(v, DCSR_EBREAKH, state.dcsr.ebreakh);
 847         v = set_field(v, DCSR_EBREAKS, state.dcsr.ebreaks);
 848         v = set_field(v, DCSR_EBREAKU, state.dcsr.ebreaku);
 849         v = set_field(v, DCSR_STOPCYCLE, 0);
 850         v = set_field(v, DCSR_STOPTIME, 0);
 851         v = set_field(v, DCSR_CAUSE, state.dcsr.cause);
 852         v = set_field(v, DCSR_STEP, state.dcsr.step);
 853         v = set_field(v, DCSR_PRV, state.dcsr.prv);
 854         return v;
 855       }
 856     case CSR_DPC:
 857       return state.dpc & pc_alignment_mask();
 858     case CSR_DSCRATCH:
 859       return state.dscratch;
 860   }
 861   throw trap_illegal_instruction(0);
 862 }
 863
 864 reg_t illegal_instruction(processor_t* p, insn_t insn, reg_t pc)
 865 {
 866   throw trap_illegal_instruction(0);
 867 }
 868
 869 insn_func_t processor_t::decode_insn(insn_t insn)
 870 {
 871   // look up opcode in hash table
 872   size_t idx = insn.bits() % OPCODE_CACHE_SIZE;
 873   insn_desc_t desc = opcode_cache[idx];
 874
 875   if (unlikely(insn.bits() != desc.match)) {
 876     // fall back to linear search
 877     insn_desc_t* p = &instructions[0];
 878     while ((insn.bits() & p->mask) != p->match)
 879       p++;
 880     desc = *p;
 881
 882     if (p->mask != 0 && p > &instructions[0]) {
 883       if (p->match != (p-1)->match && p->match != (p+1)->match) {
 884         // move to front of opcode list to reduce miss penalty
 885         while (--p >= &instructions[0])
 886           *(p+1) = *p;
 887         instructions[0] = desc;
 888       }
 889     }
 890
 891     opcode_cache[idx] = desc;
 892     opcode_cache[idx].match = insn.bits();
 893   }
 894
 895   return xlen == 64 ? desc.rv64 : desc.rv32;
 896 }
 897
 898 void processor_t::register_insn(insn_desc_t desc)
 899 {
 900   instructions.push_back(desc);
 901 }
 902
 903 void processor_t::build_opcode_map()
 904 {
 905   struct cmp {
 906     bool operator()(const insn_desc_t& lhs, const insn_desc_t& rhs) {
 907       if (lhs.match == rhs.match)
 908         return lhs.mask > rhs.mask;
 909       return lhs.match > rhs.match;
 910     }
 911   };
 912   std::sort(instructions.begin(), instructions.end(), cmp());
 913
 914   for (size_t i = 0; i < OPCODE_CACHE_SIZE; i++)
 915     opcode_cache[i] = {0, 0, &illegal_instruction, &illegal_instruction};
 916 }
 917
 918 void processor_t::register_extension(extension_t* x)
 919 {
 920   for (auto insn : x->get_instructions())
 921     register_insn(insn);
 922   build_opcode_map();
 923   for (auto disasm_insn : x->get_disasms())
 924     disassembler->add_insn(disasm_insn);
 925   if (ext != NULL)
 926     throw std::logic_error("only one extension may be registered");
 927   ext = x;
 928   x->set_processor(this);
 929 }
 930
 931 void processor_t::register_base_instructions()
 932 {
 933   #define DECLARE_INSN(name, match, mask) \
 934     insn_bits_t name##_match = (match), name##_mask = (mask);
 935   #include "encoding.h"
 936   #undef DECLARE_INSN
 937
 938   #define DEFINE_INSN(name) \
 939     REGISTER_INSN(this, name, name##_match, name##_mask)
 940   #include "insn_list.h"
 941   #undef DEFINE_INSN
 942
 943   register_insn({0, 0, &illegal_instruction, &illegal_instruction});
 944   build_opcode_map();
 945 }
 946
 947 bool processor_t::load(reg_t addr, size_t len, uint8_t* bytes)
 948 {
 949   switch (addr)
 950   {
 951     case 0:
 952       if (len <= 4) {
 953         memset(bytes, 0, len);
 954         bytes[0] = get_field(state.mip, MIP_MSIP);
 955         return true;
 956       }
 957       break;
 958   }
 959
 960   return false;
 961 }
 962
 963 bool processor_t::store(reg_t addr, size_t len, const uint8_t* bytes)
 964 {
 965   switch (addr)
 966   {
 967     case 0:
 968       if (len <= 4) {
 969         state.mip = set_field(state.mip, MIP_MSIP, bytes[0]);
 970         return true;
 971       }
 972       break;
 973   }
 974
 975   return false;
 976 }
 977
 978 void processor_t::trigger_updated()
 979 {
 980   mmu->flush_tlb();
 981   mmu->check_triggers_fetch = false;
 982   mmu->check_triggers_load = false;
 983   mmu->check_triggers_store = false;
 984
 985   for (unsigned i = 0; i < state.num_triggers; i++) {
 986     if (state.mcontrol[i].execute) {
 987       mmu->check_triggers_fetch = true;
 988     }
 989     if (state.mcontrol[i].load) {
 990       mmu->check_triggers_load = true;
 991     }
 992     if (state.mcontrol[i].store) {
 993       mmu->check_triggers_store = true;
 994     }
 995   }
 996 }