1 // See LICENSE for license details.
19 #include "sv_insn_redirect.h"
25 processor_t::processor_t(const char* isa
, simif_t
* sim
, uint32_t id
,
27 : debug(false), halt_request(false), sim(sim
), ext(NULL
), id(id
),
28 halt_on_reset(halt_on_reset
), last_pc(1), executions(1)
33 parse_isa_string(isa
);
34 register_base_instructions();
37 mmu
= new sv_mmu_t(sim
, this);
39 mmu
= new mmu_t(sim
, this);
42 disassembler
= new disassembler_t(max_xlen
);
44 for (auto disasm_insn
: ext
->get_disasms())
45 disassembler
->add_insn(disasm_insn
);
50 processor_t::~processor_t()
52 #ifdef RISCV_ENABLE_HISTOGRAM
53 if (histogram_enabled
)
55 fprintf(stderr
, "PC Histogram size:%zu\n", pc_histogram
.size());
56 for (auto it
: pc_histogram
)
57 fprintf(stderr
, "%0" PRIx64
" %" PRIu64
"\n", it
.first
, it
.second
);
65 static void bad_isa_string(const char* isa
)
67 fprintf(stderr
, "error: bad --isa option %s\n", isa
);
71 void processor_t::parse_isa_string(const char* str
)
73 std::string lowercase
, tmp
;
74 for (const char *r
= str
; *r
; r
++)
75 lowercase
+= std::tolower(*r
);
77 const char* p
= lowercase
.c_str();
78 const char* all_subsets
= "imafdqc";
81 state
.misa
= reg_t(2) << 62;
83 if (strncmp(p
, "rv32", 4) == 0)
84 max_xlen
= 32, state
.misa
= reg_t(1) << 30, p
+= 4;
85 else if (strncmp(p
, "rv64", 4) == 0)
87 else if (strncmp(p
, "rv", 2) == 0)
92 } else if (*p
== 'g') { // treat "G" as "IMAFD"
93 tmp
= std::string("imafd") + (p
+1);
95 } else if (*p
!= 'i') {
99 isa_string
= "rv" + std::to_string(max_xlen
) + p
;
100 state
.misa
|= 1L << ('s' - 'a'); // advertise support for supervisor mode
101 state
.misa
|= 1L << ('u' - 'a'); // advertise support for user mode
104 state
.misa
|= 1L << (*p
- 'a');
106 if (auto next
= strchr(all_subsets
, *p
)) {
107 all_subsets
= next
+ 1;
109 } else if (*p
== 'x') {
110 const char* ext
= p
+1, *end
= ext
;
111 while (islower(*end
))
113 register_extension(find_extension(std::string(ext
, end
- ext
).c_str())());
120 if (supports_extension('D') && !supports_extension('F'))
123 if (supports_extension('Q') && !supports_extension('D'))
126 if (supports_extension('Q') && max_xlen
< 64)
129 max_isa
= state
.misa
;
132 void state_t::reset(reg_t max_isa
)
134 memset(this, 0, sizeof(*this));
139 for (unsigned int i
= 0; i
< num_triggers
; i
++)
140 mcontrol
[i
].type
= 2;
142 // set SV CSR banks to default (full) sizes
149 void sv_shape_t::setup_map()
152 int lims
[3] = {xsz
, ysz
, zsz
};
153 int idxs
[3] = {0,0,0};
156 case SV_SHAPE_PERM_XYZ
: order
[0] = 0; order
[1] = 1; order
[2] = 2; break;
157 case SV_SHAPE_PERM_XZY
: order
[0] = 0; order
[1] = 2; order
[2] = 1; break;
158 case SV_SHAPE_PERM_YXZ
: order
[0] = 1; order
[1] = 0; order
[2] = 2; break;
159 case SV_SHAPE_PERM_YZX
: order
[0] = 1; order
[1] = 2; order
[2] = 0; break;
160 case SV_SHAPE_PERM_ZXY
: order
[0] = 2; order
[1] = 0; order
[2] = 1; break;
161 case SV_SHAPE_PERM_ZYX
: order
[0] = 2; order
[1] = 1; order
[2] = 0; break;
162 default: throw trap_illegal_instruction(0);
164 for (int i
= 0; i
< 128; i
++)
166 uint8_t new_idx
= idxs
[0] + idxs
[1] * xsz
+ idxs
[2] * xsz
* ysz
;
168 for (int j
= 0; j
< 3; j
++)
170 idxs
[order
[j
]] = idxs
[order
[j
]] + 1;
171 if (idxs
[order
[j
]] != lims
[order
[j
]]) {
179 int state_t::sv_csr_sz()
187 sv_csr_t
&state_t::sv()
196 sv_shape_t
* state_t::get_shape(reg_t reg
, bool pred
)
198 if (prv
== PRV_M
|| prv
== PRV_S
|| reg
== 0) {
201 for (int i
= 0; i
< 3; i
++) {
202 if (remap
[i
].regidx
== reg
&& remap
[i
].pred
== pred
) {
209 void processor_t::set_debug(bool value
)
213 ext
->set_debug(value
);
216 void processor_t::set_histogram(bool value
)
218 histogram_enabled
= value
;
219 #ifndef RISCV_ENABLE_HISTOGRAM
221 fprintf(stderr
, "PC Histogram support has not been properly enabled;");
222 fprintf(stderr
, " please re-build the riscv-isa-run project using \"configure --enable-histogram\".\n");
227 void processor_t::reset()
229 state
.reset(max_isa
);
230 state
.dcsr
.halt
= halt_on_reset
;
231 halt_on_reset
= false;
232 set_csr(CSR_MSTATUS
, state
.mstatus
);
235 ext
->reset(); // reset the extension
241 // Count number of contiguous 0 bits starting from the LSB.
242 static int ctz(reg_t val
)
246 while ((val
& 1) == 0)
251 void processor_t::take_interrupt(reg_t pending_interrupts
)
253 reg_t mie
= get_field(state
.mstatus
, MSTATUS_MIE
);
254 reg_t m_enabled
= state
.prv
< PRV_M
|| (state
.prv
== PRV_M
&& mie
);
255 reg_t enabled_interrupts
= pending_interrupts
& ~state
.mideleg
& -m_enabled
;
257 reg_t sie
= get_field(state
.mstatus
, MSTATUS_SIE
);
258 reg_t s_enabled
= state
.prv
< PRV_S
|| (state
.prv
== PRV_S
&& sie
);
259 // M-ints have highest priority; consider S-ints only if no M-ints pending
260 if (enabled_interrupts
== 0)
261 enabled_interrupts
= pending_interrupts
& state
.mideleg
& -s_enabled
;
263 if (state
.dcsr
.cause
== 0 && enabled_interrupts
) {
264 // nonstandard interrupts have highest priority
265 if (enabled_interrupts
>> IRQ_M_EXT
)
266 enabled_interrupts
= enabled_interrupts
>> IRQ_M_EXT
<< IRQ_M_EXT
;
267 // external interrupts have next-highest priority
268 else if (enabled_interrupts
& (MIP_MEIP
| MIP_SEIP
))
269 enabled_interrupts
= enabled_interrupts
& (MIP_MEIP
| MIP_SEIP
);
270 // software interrupts have next-highest priority
271 else if (enabled_interrupts
& (MIP_MSIP
| MIP_SSIP
))
272 enabled_interrupts
= enabled_interrupts
& (MIP_MSIP
| MIP_SSIP
);
273 // timer interrupts have next-highest priority
274 else if (enabled_interrupts
& (MIP_MTIP
| MIP_STIP
))
275 enabled_interrupts
= enabled_interrupts
& (MIP_MTIP
| MIP_STIP
);
279 throw trap_t(((reg_t
)1 << (max_xlen
-1)) | ctz(enabled_interrupts
));
283 static int xlen_to_uxl(int xlen
)
292 reg_t
processor_t::legalize_privilege(reg_t prv
)
294 assert(prv
<= PRV_M
);
296 if (!supports_extension('U'))
299 if (prv
== PRV_H
|| !supports_extension('S'))
305 void processor_t::set_privilege(reg_t prv
)
308 state
.prv
= legalize_privilege(prv
);
311 void processor_t::enter_debug_mode(uint8_t cause
)
313 state
.dcsr
.cause
= cause
;
314 state
.dcsr
.prv
= state
.prv
;
315 set_privilege(PRV_M
);
316 state
.dpc
= state
.pc
;
317 state
.pc
= DEBUG_ROM_ENTRY
;
320 void processor_t::take_trap(trap_t
& t
, reg_t epc
)
323 fprintf(stderr
, "core %3d: exception %s, epc 0x%016" PRIx64
"\n",
326 fprintf(stderr
, "core %3d: tval 0x%016" PRIx64
"\n", id
,
330 if (state
.dcsr
.cause
) {
331 if (t
.cause() == CAUSE_BREAKPOINT
) {
332 state
.pc
= DEBUG_ROM_ENTRY
;
334 state
.pc
= DEBUG_ROM_TVEC
;
339 if (t
.cause() == CAUSE_BREAKPOINT
&& (
340 (state
.prv
== PRV_M
&& state
.dcsr
.ebreakm
) ||
341 (state
.prv
== PRV_S
&& state
.dcsr
.ebreaks
) ||
342 (state
.prv
== PRV_U
&& state
.dcsr
.ebreaku
))) {
343 enter_debug_mode(DCSR_CAUSE_SWBP
);
347 // by default, trap to M-mode, unless delegated to S-mode
348 reg_t bit
= t
.cause();
349 reg_t deleg
= state
.medeleg
;
350 bool interrupt
= (bit
& ((reg_t
)1 << (max_xlen
-1))) != 0;
352 deleg
= state
.mideleg
, bit
&= ~((reg_t
)1 << (max_xlen
-1));
353 if (state
.prv
<= PRV_S
&& bit
< max_xlen
&& ((deleg
>> bit
) & 1)) {
354 // handle the trap in S-mode
355 state
.pc
= state
.stvec
;
356 state
.scause
= t
.cause();
358 state
.stval
= t
.get_tval();
360 reg_t s
= state
.mstatus
;
361 s
= set_field(s
, MSTATUS_SPIE
, get_field(s
, MSTATUS_SIE
));
362 s
= set_field(s
, MSTATUS_SPP
, state
.prv
);
363 s
= set_field(s
, MSTATUS_SIE
, 0);
364 set_csr(CSR_MSTATUS
, s
);
365 set_privilege(PRV_S
);
367 reg_t vector
= (state
.mtvec
& 1) && interrupt
? 4*bit
: 0;
368 state
.pc
= (state
.mtvec
& ~(reg_t
)1) + vector
;
370 state
.mcause
= t
.cause();
371 state
.mtval
= t
.get_tval();
373 reg_t s
= state
.mstatus
;
374 s
= set_field(s
, MSTATUS_MPIE
, get_field(s
, MSTATUS_MIE
));
375 s
= set_field(s
, MSTATUS_MPP
, state
.prv
);
376 s
= set_field(s
, MSTATUS_MIE
, 0);
377 set_csr(CSR_MSTATUS
, s
);
378 set_privilege(PRV_M
);
382 void processor_t::disasm(insn_t insn
)
384 uint64_t bits
= insn
.bits() & ((1ULL << (8 * insn_length(insn
.bits()))) - 1);
385 if (last_pc
!= state
.pc
|| last_bits
!= bits
) {
386 if (executions
!= 1) {
387 fprintf(stderr
, "core %3d: Executed %" PRIx64
" times\n", id
, executions
);
390 fprintf(stderr
, "core %3d: 0x%016" PRIx64
" (0x%08" PRIx64
") %s\n",
391 id
, state
.pc
, bits
, disassembler
->disassemble(insn
).c_str());
400 int processor_t::paddr_bits()
402 assert(xlen
== max_xlen
);
403 return max_xlen
== 64 ? 50 : 34;
406 void state_t::get_csr_start_end(int &start
, int &end
)
408 start
= sv().state_bank
* 4;
409 end
= start
+ (1 << (sv().state_size
+1));
410 start
= std::min(sv_csr_sz(), start
);
411 end
= std::min(sv_csr_sz(), end
);
412 fprintf(stderr
, "sv state csr start/end: %d %d\n", start
, end
);
415 void state_t::sv_csr_reg_unpack()
417 // okaaay and now "unpack" the CAM to make it easier to use. this
418 // approach is not designed to be efficient right now. optimise later
419 // first clear the old tables
420 memset(sv().sv_int_tb
, 0, sizeof(sv().sv_int_tb
));
421 memset(sv().sv_fp_tb
, 0, sizeof(sv().sv_fp_tb
));
422 // now walk the CAM and unpack it
425 get_csr_start_end(start
, end
);
426 for (int i
= start
; i
< end
; i
++)
428 union sv_reg_csr_entry
*c
= &sv().sv_csrs
[i
];
429 uint64_t idx
= c
->b
.regkey
;
435 // XXX damn. this basically duplicates sv_insn_t::get_regentry.
438 r
= &sv().sv_int_tb
[idx
];
442 r
= &sv().sv_fp_tb
[idx
];
444 r
->elwidth
= c
->b
.elwidth
;
445 r
->regidx
= c
->b
.regidx
;
446 r
->isvec
= c
->b
.isvec
;
448 fprintf(stderr
, "setting REGCFG type:%d isvec:%d %d %d\n",
449 c
->b
.type
, r
->isvec
, (int)idx
, (int)r
->regidx
);
453 void state_t::sv_csr_pred_unpack()
455 memset(sv().sv_pred_int_tb
, 0, sizeof(sv().sv_pred_int_tb
));
456 memset(sv().sv_pred_fp_tb
, 0, sizeof(sv().sv_pred_fp_tb
));
459 get_csr_start_end(start
, end
);
460 for (int i
= start
; i
< end
; i
++)
462 union sv_pred_csr_entry
*c
= &sv().sv_pred_csrs
[i
];
463 uint64_t idx
= c
->b
.regkey
;
469 // XXX damn. this basically duplicates sv_insn_t::get_predentry.
472 r
= &sv().sv_pred_int_tb
[idx
];
476 r
= &sv().sv_pred_fp_tb
[idx
];
478 r
->regidx
= c
->b
.regidx
;
481 r
->ffirst
= c
->b
.ffirst
;
483 fprintf(stderr
, "setting PREDCFG %d type:%d zero:%d %d %d\n",
484 i
, c
->b
.type
, r
->zero
, (int)idx
, (int)r
->regidx
);
488 reg_t
processor_t::set_csr(int which
, reg_t val
, bool imm_mode
)
490 reg_t old_val
= get_csr(which
);
491 val
= _zext_xlen(val
);
492 reg_t delegable_ints
= MIP_SSIP
| MIP_STIP
| MIP_SEIP
493 | ((ext
!= NULL
) << IRQ_COP
);
494 reg_t all_ints
= delegable_ints
| MIP_MSIP
| MIP_MTIP
;
495 fprintf(stderr
, "set CSR %x %lx\n", which
, val
);
500 state
.sv().mvl
= std::min(val
+1, (uint64_t)64); // limited to XLEN width
501 old_val
= state
.sv().mvl
- 1;
502 // TODO XXX throw exception if val == 0
503 fprintf(stderr
, "set MVL %lx\n", state
.sv().mvl
);
507 // bits 0-5: mvl - 6-11: vl - 12-17: srcoffs - 18-23: destoffs
508 set_csr(CSR_USVMVL
, get_field(val
, SV_STATE_VL
)+1);
509 set_csr(CSR_USVVL
, get_field(val
, SV_STATE_MVL
)+1);
510 set_csr(CSR_USVSUBVL
, get_field(val
, SV_STATE_SUBVL
)+1);
511 // decode (and limit) src/dest VL offsets
512 reg_t srcoffs
= get_field(val
, SV_STATE_SRCOFFS
);
513 reg_t destoffs
= get_field(val
, SV_STATE_DESTOFFS
);
514 state
.sv().srcoffs
= std::min(srcoffs
, state
.sv().vl
-1);
515 state
.sv().destoffs
= std::min(destoffs
, state
.sv().vl
-1);
516 // decode (and limit) src/dest SUBVL offsets
517 reg_t subsrcoffs
= get_field(val
, SV_STATE_SSVOFFS
);
518 reg_t subdestoffs
= get_field(val
, SV_STATE_DSVOFFS
);
519 state
.sv().ssvoffs
= std::min(subsrcoffs
, state
.sv().subvl
-1);
520 state
.sv().dsvoffs
= std::min(subdestoffs
, state
.sv().subvl
-1);
521 //int state_bank = get_field(val, SV_STATE_BANK);
522 //int state_size = get_field(val, SV_STATE_SIZE);
523 //set_csr(CSR_USVCFG, state_bank | (state_size << 3));
528 int old_bank
= state
.sv().state_bank
;
529 int old_size
= state
.sv().state_size
;
530 state
.sv().state_bank
= get_field(val
, SV_CFG_BANK
);
531 state
.sv().state_size
= get_field(val
, SV_CFG_SIZE
);
532 if (old_bank
!= state
.sv().state_bank
||
533 old_size
!= state
.sv().state_size
)
535 // if the bank or size is changed, the csrs that are enabled
536 // also changes. easiest thing in software: recalculate them all
537 state
.sv_csr_pred_unpack();
538 state
.sv_csr_reg_unpack();
543 state
.sv().subvl
= std::max(1, std::min(4, (int)val
));
544 old_val
= state
.sv().subvl
;
545 // TODO XXX throw exception if val attempted to be set == 0
546 fprintf(stderr
, "set VL %lx\n", state
.sv().vl
);
549 state
.sv().vl
= std::min(state
.sv().mvl
, val
+ 1);
550 old_val
= state
.sv().mvl
- 1;
551 // TODO XXX throw exception if val == 0
552 fprintf(stderr
, "set VL %lx\n", state
.sv().vl
);
557 bool top
= (which
== CSR_SVREGTOP
);
558 uint64_t v
= (uint64_t)val
;
559 fprintf(stderr
, "set SVREG %d %lx\n", top
, v
);
562 state
.get_csr_start_end(start
, end
);
563 uint64_t res_old
= 0;
564 int num_entries
= val
& 0xf;
565 int max_xlen_entries
= (xlen
== 64) ? 4 : 2;
567 num_entries
= max_xlen_entries
;
569 // read 2 16-bit entries for RV32, 4 16-bit entries for RV64
571 for (int i
= 0; i
< num_entries
; i
++) {
574 uint64_t mask
= 0xffffUL
<< (i
*16UL);
575 svcfg
= get_field(v
, mask
);
576 fprintf(stderr
, "SVREG mask %lx cfg %lx\n", mask
, svcfg
);
577 if (!svcfg
&& i
> 0) {
581 // see regpush on how this works.
582 uint64_t res
= state
.sv().regpush(svcfg
, end
, top
);
584 res_old
|= res
<< (popidx
* 16UL);
586 if (popidx
== max_xlen_entries
) {
592 state
.sv_csr_reg_unpack();
604 // comments removed as it's near-identical to the regs version
606 uint64_t v
= (uint64_t)val
;
607 int tbidx
= (which
- CSR_SVPREDCFG0
) * 2;
608 fprintf(stderr
, "set PREDCFG %d %lx\n", tbidx
, v
);
609 state
.sv().sv_pred_csrs
[tbidx
].u
= get_field(v
, 0xffff);
610 state
.sv().sv_pred_csrs
[tbidx
+1].u
= get_field(v
, 0xffff0000);
614 state
.sv().sv_pred_csrs
[tbidx
+2].u
= get_field(v
, 0xffffUL
<<32);
615 state
.sv().sv_pred_csrs
[tbidx
+3].u
= get_field(v
, 0xffffUL
<<48);
618 for (int i
= tbidx
+clroffset
; i
< 16; i
++)
620 state
.sv().sv_pred_csrs
[i
].u
= 0;
622 state
.sv_csr_pred_unpack();
627 state
.remap
[0].regidx
= get_field(val
, SV_REMAP_REGIDX0
);
628 state
.remap
[1].regidx
= get_field(val
, SV_REMAP_REGIDX1
);
629 state
.remap
[2].regidx
= get_field(val
, SV_REMAP_REGIDX2
);
630 state
.remap
[0].pred
= get_field(val
, SV_REMAP_PRED0
);
631 state
.remap
[1].pred
= get_field(val
, SV_REMAP_PRED1
);
632 state
.remap
[2].pred
= get_field(val
, SV_REMAP_PRED2
);
633 state
.remap
[0].shape
= get_field(val
, SV_REMAP_SHAPE0
);
634 state
.remap
[1].shape
= get_field(val
, SV_REMAP_SHAPE1
);
635 state
.remap
[2].shape
= get_field(val
, SV_REMAP_SHAPE2
);
642 int shapeidx
= which
- CSR_USHAPE0
;
643 state
.shape
[shapeidx
].xsz
= get_field(val
, SV_SHAPE_XDIM
) + 1;
644 state
.shape
[shapeidx
].ysz
= get_field(val
, SV_SHAPE_YDIM
) + 1;
645 state
.shape
[shapeidx
].zsz
= get_field(val
, SV_SHAPE_ZDIM
) + 1;
646 state
.shape
[shapeidx
].offs
= (get_field(val
, (1<<7 )) ? 0x1 : 0) |
647 (get_field(val
, (1<<15)) ? 0x2 : 0) |
648 (get_field(val
, (1<<23)) ? 0x4 : 0);
649 state
.shape
[shapeidx
].permute
= get_field(val
, SV_SHAPE_PERM
);
650 state
.shape
[shapeidx
].setup_map();
651 fprintf(stderr
, "sv shape %d x %d y %d z %d offs %d perm %d\n",
653 state
.shape
[shapeidx
].xsz
,
654 state
.shape
[shapeidx
].ysz
,
655 state
.shape
[shapeidx
].zsz
,
656 state
.shape
[shapeidx
].offs
,
657 state
.shape
[shapeidx
].permute
);
663 state
.fflags
= val
& (FSR_AEXC
>> FSR_AEXC_SHIFT
);
667 state
.frm
= val
& (FSR_RD
>> FSR_RD_SHIFT
);
671 state
.fflags
= (val
& FSR_AEXC
) >> FSR_AEXC_SHIFT
;
672 state
.frm
= (val
& FSR_RD
) >> FSR_RD_SHIFT
;
675 if ((val
^ state
.mstatus
) &
676 (MSTATUS_MPP
| MSTATUS_MPRV
| MSTATUS_SUM
| MSTATUS_MXR
))
679 reg_t mask
= MSTATUS_SIE
| MSTATUS_SPIE
| MSTATUS_MIE
| MSTATUS_MPIE
680 | MSTATUS_FS
| MSTATUS_MPRV
| MSTATUS_SUM
681 | MSTATUS_MXR
| MSTATUS_TW
| MSTATUS_TVM
682 | MSTATUS_TSR
| MSTATUS_UXL
| MSTATUS_SXL
|
683 (ext
? MSTATUS_XS
: 0);
685 reg_t requested_mpp
= legalize_privilege(get_field(val
, MSTATUS_MPP
));
686 state
.mstatus
= set_field(state
.mstatus
, MSTATUS_MPP
, requested_mpp
);
687 if (supports_extension('S'))
690 state
.mstatus
= (state
.mstatus
& ~mask
) | (val
& mask
);
692 bool dirty
= (state
.mstatus
& MSTATUS_FS
) == MSTATUS_FS
;
693 dirty
|= (state
.mstatus
& MSTATUS_XS
) == MSTATUS_XS
;
695 state
.mstatus
= set_field(state
.mstatus
, MSTATUS32_SD
, dirty
);
697 state
.mstatus
= set_field(state
.mstatus
, MSTATUS64_SD
, dirty
);
699 state
.mstatus
= set_field(state
.mstatus
, MSTATUS_UXL
, xlen_to_uxl(max_xlen
));
700 state
.mstatus
= set_field(state
.mstatus
, MSTATUS_UXL
, xlen_to_uxl(max_xlen
));
701 state
.mstatus
= set_field(state
.mstatus
, MSTATUS_SXL
, xlen_to_uxl(max_xlen
));
702 // U-XLEN == S-XLEN == M-XLEN
707 reg_t mask
= MIP_SSIP
| MIP_STIP
;
708 state
.mip
= (state
.mip
& ~mask
) | (val
& mask
);
712 state
.mie
= (state
.mie
& ~all_ints
) | (val
& all_ints
);
715 state
.mideleg
= (state
.mideleg
& ~delegable_ints
) | (val
& delegable_ints
);
719 (1 << CAUSE_MISALIGNED_FETCH
) |
720 (1 << CAUSE_BREAKPOINT
) |
721 (1 << CAUSE_USER_ECALL
) |
722 (1 << CAUSE_FETCH_PAGE_FAULT
) |
723 (1 << CAUSE_LOAD_PAGE_FAULT
) |
724 (1 << CAUSE_STORE_PAGE_FAULT
);
725 state
.medeleg
= (state
.medeleg
& ~mask
) | (val
& mask
);
731 state
.minstret
= (state
.minstret
>> 32 << 32) | (val
& 0xffffffffU
);
733 state
.minstret
= val
;
734 // The ISA mandates that if an instruction writes instret, the write
735 // takes precedence over the increment to instret. However, Spike
736 // unconditionally increments instret after executing an instruction.
737 // Correct for this artifact by decrementing instret here.
742 state
.minstret
= (val
<< 32) | (state
.minstret
<< 32 >> 32);
743 state
.minstret
--; // See comment above.
746 state
.scounteren
= val
;
749 state
.mcounteren
= val
;
752 reg_t mask
= SSTATUS_SIE
| SSTATUS_SPIE
| SSTATUS_SPP
| SSTATUS_FS
753 | SSTATUS_XS
| SSTATUS_SUM
| SSTATUS_MXR
;
754 return set_csr(CSR_MSTATUS
, (state
.mstatus
& ~mask
) | (val
& mask
));
757 reg_t mask
= MIP_SSIP
& state
.mideleg
;
758 return set_csr(CSR_MIP
, (state
.mip
& ~mask
) | (val
& mask
));
761 return set_csr(CSR_MIE
,
762 (state
.mie
& ~state
.mideleg
) | (val
& state
.mideleg
));
766 state
.satp
= val
& (SATP32_PPN
| SATP32_MODE
);
767 if (max_xlen
== 64 && (get_field(val
, SATP64_MODE
) == SATP_MODE_OFF
||
768 get_field(val
, SATP64_MODE
) == SATP_MODE_SV39
||
769 get_field(val
, SATP64_MODE
) == SATP_MODE_SV48
))
770 state
.satp
= val
& (SATP64_PPN
| SATP64_MODE
);
773 case CSR_SEPC
: state
.sepc
= val
& ~(reg_t
)1; break;
774 case CSR_STVEC
: state
.stvec
= val
>> 2 << 2; break;
775 case CSR_SSCRATCH
: state
.sscratch
= val
; break;
776 case CSR_SCAUSE
: state
.scause
= val
; break;
777 case CSR_STVAL
: state
.stval
= val
; break;
778 case CSR_MEPC
: state
.mepc
= val
& ~(reg_t
)1; break;
779 case CSR_MTVEC
: state
.mtvec
= val
& ~(reg_t
)2; break;
780 case CSR_MSCRATCH
: state
.mscratch
= val
; break;
781 case CSR_MCAUSE
: state
.mcause
= val
; break;
782 case CSR_MTVAL
: state
.mtval
= val
; break;
784 // the write is ignored if increasing IALIGN would misalign the PC
785 if (!(val
& (1L << ('C' - 'A'))) && (state
.pc
& 2))
788 if (!(val
& (1L << ('F' - 'A'))))
789 val
&= ~(1L << ('D' - 'A'));
791 // allow MAFDC bits in MISA to be modified
793 mask
|= 1L << ('M' - 'A');
794 mask
|= 1L << ('A' - 'A');
795 mask
|= 1L << ('F' - 'A');
796 mask
|= 1L << ('D' - 'A');
797 mask
|= 1L << ('C' - 'A');
800 state
.misa
= (val
& mask
) | (state
.misa
& ~mask
);
804 if (val
< state
.num_triggers
) {
810 mcontrol_t
*mc
= &state
.mcontrol
[state
.tselect
];
811 if (mc
->dmode
&& !state
.dcsr
.cause
) {
814 mc
->dmode
= get_field(val
, MCONTROL_DMODE(xlen
));
815 mc
->select
= get_field(val
, MCONTROL_SELECT
);
816 mc
->timing
= get_field(val
, MCONTROL_TIMING
);
817 mc
->action
= (mcontrol_action_t
) get_field(val
, MCONTROL_ACTION
);
818 mc
->chain
= get_field(val
, MCONTROL_CHAIN
);
819 mc
->match
= (mcontrol_match_t
) get_field(val
, MCONTROL_MATCH
);
820 mc
->m
= get_field(val
, MCONTROL_M
);
821 mc
->h
= get_field(val
, MCONTROL_H
);
822 mc
->s
= get_field(val
, MCONTROL_S
);
823 mc
->u
= get_field(val
, MCONTROL_U
);
824 mc
->execute
= get_field(val
, MCONTROL_EXECUTE
);
825 mc
->store
= get_field(val
, MCONTROL_STORE
);
826 mc
->load
= get_field(val
, MCONTROL_LOAD
);
827 // Assume we're here because of csrw.
834 if (state
.mcontrol
[state
.tselect
].dmode
&& !state
.dcsr
.cause
) {
837 if (state
.tselect
< state
.num_triggers
) {
838 state
.tdata2
[state
.tselect
] = val
;
842 state
.dcsr
.prv
= get_field(val
, DCSR_PRV
);
843 state
.dcsr
.step
= get_field(val
, DCSR_STEP
);
844 // TODO: ndreset and fullreset
845 state
.dcsr
.ebreakm
= get_field(val
, DCSR_EBREAKM
);
846 state
.dcsr
.ebreakh
= get_field(val
, DCSR_EBREAKH
);
847 state
.dcsr
.ebreaks
= get_field(val
, DCSR_EBREAKS
);
848 state
.dcsr
.ebreaku
= get_field(val
, DCSR_EBREAKU
);
849 state
.dcsr
.halt
= get_field(val
, DCSR_HALT
);
852 state
.dpc
= val
& ~(reg_t
)1;
855 state
.dscratch
= val
;
861 reg_t
processor_t::get_csr(int which
)
863 uint32_t ctr_en
= -1;
864 if (state
.prv
< PRV_M
)
865 ctr_en
&= state
.mcounteren
;
866 if (state
.prv
< PRV_S
)
867 ctr_en
&= state
.scounteren
;
868 bool ctr_ok
= (ctr_en
>> (which
& 31)) & 1;
871 if (which
>= CSR_HPMCOUNTER3
&& which
<= CSR_HPMCOUNTER31
)
873 if (xlen
== 32 && which
>= CSR_HPMCOUNTER3H
&& which
<= CSR_HPMCOUNTER31H
)
876 if (which
>= CSR_MHPMCOUNTER3
&& which
<= CSR_MHPMCOUNTER31
)
878 if (xlen
== 32 && which
>= CSR_MHPMCOUNTER3H
&& which
<= CSR_MHPMCOUNTER31H
)
880 if (which
>= CSR_MHPMEVENT3
&& which
<= CSR_MHPMEVENT31
)
887 return state
.sv().vl
;
889 return (state
.sv().state_bank
) | (state
.sv().state_size
<<3);
891 return (state
.sv().vl
-1) | ((state
.sv().mvl
-1)<<6) |
892 (state
.sv().srcoffs
<<12) | (state
.sv().destoffs
<<18) |
893 (state
.sv().state_bank
<<24) | (state
.sv().state_size
<<26);
895 return state
.sv().mvl
;
898 return 0;// XXX TODO: return correct entry
907 return 0;// XXX TODO: return correct entry
909 return 0;// XXX TODO: return correct entry
913 return 0;// XXX TODO: return correct entry
917 if (!supports_extension('F'))
922 if (!supports_extension('F'))
927 if (!supports_extension('F'))
929 return (state
.fflags
<< FSR_AEXC_SHIFT
) | (state
.frm
<< FSR_RD_SHIFT
);
933 return state
.minstret
;
937 return state
.minstret
;
940 if (ctr_ok
&& xlen
== 32)
941 return state
.minstret
>> 32;
946 return state
.minstret
>> 32;
948 case CSR_SCOUNTEREN
: return state
.scounteren
;
949 case CSR_MCOUNTEREN
: return state
.mcounteren
;
951 reg_t mask
= SSTATUS_SIE
| SSTATUS_SPIE
| SSTATUS_SPP
| SSTATUS_FS
952 | SSTATUS_XS
| SSTATUS_SUM
| SSTATUS_MXR
| SSTATUS_UXL
;
953 reg_t sstatus
= state
.mstatus
& mask
;
954 if ((sstatus
& SSTATUS_FS
) == SSTATUS_FS
||
955 (sstatus
& SSTATUS_XS
) == SSTATUS_XS
)
956 sstatus
|= (xlen
== 32 ? SSTATUS32_SD
: SSTATUS64_SD
);
959 case CSR_SIP
: return state
.mip
& state
.mideleg
;
960 case CSR_SIE
: return state
.mie
& state
.mideleg
;
961 case CSR_SEPC
: return state
.sepc
& pc_alignment_mask();
962 case CSR_STVAL
: return state
.stval
;
963 case CSR_STVEC
: return state
.stvec
;
966 return state
.scause
| ((state
.scause
>> (max_xlen
-1)) << (xlen
-1));
969 if (get_field(state
.mstatus
, MSTATUS_TVM
))
970 require_privilege(PRV_M
);
972 case CSR_SSCRATCH
: return state
.sscratch
;
973 case CSR_MSTATUS
: return state
.mstatus
;
974 case CSR_MIP
: return state
.mip
;
975 case CSR_MIE
: return state
.mie
;
976 case CSR_MEPC
: return state
.mepc
& pc_alignment_mask();
977 case CSR_MSCRATCH
: return state
.mscratch
;
978 case CSR_MCAUSE
: return state
.mcause
;
979 case CSR_MTVAL
: return state
.mtval
;
980 case CSR_MISA
: return state
.misa
;
981 case CSR_MARCHID
: return 0;
982 case CSR_MIMPID
: return 0;
983 case CSR_MVENDORID
: return 0;
984 case CSR_MHARTID
: return id
;
985 case CSR_MTVEC
: return state
.mtvec
;
986 case CSR_MEDELEG
: return state
.medeleg
;
987 case CSR_MIDELEG
: return state
.mideleg
;
988 case CSR_TSELECT
: return state
.tselect
;
990 if (state
.tselect
< state
.num_triggers
) {
992 mcontrol_t
*mc
= &state
.mcontrol
[state
.tselect
];
993 v
= set_field(v
, MCONTROL_TYPE(xlen
), mc
->type
);
994 v
= set_field(v
, MCONTROL_DMODE(xlen
), mc
->dmode
);
995 v
= set_field(v
, MCONTROL_MASKMAX(xlen
), mc
->maskmax
);
996 v
= set_field(v
, MCONTROL_SELECT
, mc
->select
);
997 v
= set_field(v
, MCONTROL_TIMING
, mc
->timing
);
998 v
= set_field(v
, MCONTROL_ACTION
, mc
->action
);
999 v
= set_field(v
, MCONTROL_CHAIN
, mc
->chain
);
1000 v
= set_field(v
, MCONTROL_MATCH
, mc
->match
);
1001 v
= set_field(v
, MCONTROL_M
, mc
->m
);
1002 v
= set_field(v
, MCONTROL_H
, mc
->h
);
1003 v
= set_field(v
, MCONTROL_S
, mc
->s
);
1004 v
= set_field(v
, MCONTROL_U
, mc
->u
);
1005 v
= set_field(v
, MCONTROL_EXECUTE
, mc
->execute
);
1006 v
= set_field(v
, MCONTROL_STORE
, mc
->store
);
1007 v
= set_field(v
, MCONTROL_LOAD
, mc
->load
);
1014 if (state
.tselect
< state
.num_triggers
) {
1015 return state
.tdata2
[state
.tselect
];
1020 case CSR_TDATA3
: return 0;
1024 v
= set_field(v
, DCSR_XDEBUGVER
, 1);
1025 v
= set_field(v
, DCSR_EBREAKM
, state
.dcsr
.ebreakm
);
1026 v
= set_field(v
, DCSR_EBREAKH
, state
.dcsr
.ebreakh
);
1027 v
= set_field(v
, DCSR_EBREAKS
, state
.dcsr
.ebreaks
);
1028 v
= set_field(v
, DCSR_EBREAKU
, state
.dcsr
.ebreaku
);
1029 v
= set_field(v
, DCSR_STOPCYCLE
, 0);
1030 v
= set_field(v
, DCSR_STOPTIME
, 0);
1031 v
= set_field(v
, DCSR_CAUSE
, state
.dcsr
.cause
);
1032 v
= set_field(v
, DCSR_STEP
, state
.dcsr
.step
);
1033 v
= set_field(v
, DCSR_PRV
, state
.dcsr
.prv
);
1037 return state
.dpc
& pc_alignment_mask();
1039 return state
.dscratch
;
1041 throw trap_illegal_instruction(0);
1044 reg_t
illegal_instruction(processor_t
* p
, insn_t insn
, reg_t pc
)
1046 throw trap_illegal_instruction(0);
1049 insn_func_t
processor_t::decode_insn(insn_t insn
)
1051 // look up opcode in hash table
1052 size_t idx
= insn
.bits() % OPCODE_CACHE_SIZE
;
1053 insn_desc_t desc
= opcode_cache
[idx
];
1055 if (unlikely(insn
.bits() != desc
.match
)) {
1056 // fall back to linear search
1057 insn_desc_t
* p
= &instructions
[0];
1058 while ((insn
.bits() & p
->mask
) != p
->match
)
1062 if (p
->mask
!= 0 && p
> &instructions
[0]) {
1063 if (p
->match
!= (p
-1)->match
&& p
->match
!= (p
+1)->match
) {
1064 // move to front of opcode list to reduce miss penalty
1065 while (--p
>= &instructions
[0])
1067 instructions
[0] = desc
;
1071 opcode_cache
[idx
] = desc
;
1072 opcode_cache
[idx
].match
= insn
.bits();
1075 return xlen
== 64 ? desc
.rv64
: desc
.rv32
;
1078 void processor_t::register_insn(insn_desc_t desc
)
1080 instructions
.push_back(desc
);
1083 void processor_t::build_opcode_map()
1086 bool operator()(const insn_desc_t
& lhs
, const insn_desc_t
& rhs
) {
1087 if (lhs
.match
== rhs
.match
)
1088 return lhs
.mask
> rhs
.mask
;
1089 return lhs
.match
> rhs
.match
;
1092 std::sort(instructions
.begin(), instructions
.end(), cmp());
1094 for (size_t i
= 0; i
< OPCODE_CACHE_SIZE
; i
++)
1095 opcode_cache
[i
] = {0, 0, &illegal_instruction
, &illegal_instruction
};
1098 void processor_t::register_extension(extension_t
* x
)
1100 for (auto insn
: x
->get_instructions())
1101 register_insn(insn
);
1103 for (auto disasm_insn
: x
->get_disasms())
1104 disassembler
->add_insn(disasm_insn
);
1106 throw std::logic_error("only one extension may be registered");
1108 x
->set_processor(this);
1111 void processor_t::register_base_instructions()
1113 #define DECLARE_INSN(name, match, mask) \
1114 insn_bits_t name##_match = (match), name##_mask = (mask);
1115 #include "encoding.h"
1118 #define DEFINE_INSN(name) \
1119 REGISTER_INSN(this, name, name##_match, name##_mask)
1120 #include "insn_list.h"
1123 register_insn({0, 0, &illegal_instruction
, &illegal_instruction
});
1127 bool processor_t::load(reg_t addr
, size_t len
, uint8_t* bytes
)
1133 memset(bytes
, 0, len
);
1134 bytes
[0] = get_field(state
.mip
, MIP_MSIP
);
1143 bool processor_t::store(reg_t addr
, size_t len
, const uint8_t* bytes
)
1149 state
.mip
= set_field(state
.mip
, MIP_MSIP
, bytes
[0]);
1158 void processor_t::trigger_updated()
1161 mmu
->check_triggers_fetch
= false;
1162 mmu
->check_triggers_load
= false;
1163 mmu
->check_triggers_store
= false;
1165 for (unsigned i
= 0; i
< state
.num_triggers
; i
++) {
1166 if (state
.mcontrol
[i
].execute
) {
1167 mmu
->check_triggers_fetch
= true;
1169 if (state
.mcontrol
[i
].load
) {
1170 mmu
->check_triggers_load
= true;
1172 if (state
.mcontrol
[i
].store
) {
1173 mmu
->check_triggers_store
= true;