Generate instruction decoder dynamically
[riscv-isa-sim.git] / riscv / riscv.mk.in
1 get_insn_list = $(shell cat $(1) | sed 's/DECLARE_INSN(\(.*\),.*,.*)/\1/')
2 get_opcode = $(shell grep \\\<$(2)\\\> $(1) | sed 's/DECLARE_INSN(.*,\(.*\),.*)/\1/')
3
4 riscv_subproject_deps = \
5 softfloat_riscv \
6 softfloat \
7
8 riscv_install_prog_srcs = \
9 spike.cc \
10 xspike.cc \
11 termios-xspike.cc \
12
13 riscv_hdrs = \
14 htif.h \
15 common.h \
16 decode.h \
17 mmu.h \
18 processor.h \
19 sim.h \
20 trap.h \
21 opcodes.h \
22 cachesim.h \
23 memtracer.h \
24
25 riscv_srcs = \
26 htif.cc \
27 processor.cc \
28 sim.cc \
29 interactive.cc \
30 trap.cc \
31 cachesim.cc \
32 mmu.cc \
33 disasm.cc \
34 $(riscv_gen_srcs) \
35
36 riscv_test_srcs =
37
38 riscv_gen_hdrs = \
39
40 riscv_gen_srcs = \
41 $(addsuffix .cc, $(call get_insn_list,$(src_dir)/riscv/opcodes.h))
42
43 $(riscv_gen_srcs): %.cc: insns/%.h insn_template.cc
44 sed 's/NAME/$(subst .cc,,$@)/' $(src_dir)/riscv/insn_template.cc | sed 's/OPCODE/$(call get_opcode,$(src_dir)/riscv/opcodes.h,$(subst .cc,,$@))/' > $@
45
46 riscv_junk = \
47 $(riscv_gen_srcs) \