Added PC histogram option.
[riscv-isa-sim.git] / riscv / rocc.cc
1 #include "rocc.h"
2 #include "trap.h"
3 #include <cstdlib>
4
5 #define customX(n) \
6 static reg_t c##n(processor_t* p, insn_t insn, reg_t pc) \
7 { \
8 require_accelerator; \
9 rocc_t* rocc = static_cast<rocc_t*>(p->get_extension()); \
10 rocc_insn_union_t u; \
11 u.i = insn; \
12 reg_t xs1 = u.r.xs1 ? RS1 : -1; \
13 reg_t xs2 = u.r.xs2 ? RS2 : -1; \
14 reg_t xd = rocc->custom##n(u.r, xs1, xs2); \
15 if (u.r.xd) \
16 WRITE_RD(xd); \
17 return pc+4; \
18 } \
19 \
20 reg_t rocc_t::custom##n(rocc_insn_t insn, reg_t xs1, reg_t xs2) \
21 { \
22 illegal_instruction(); \
23 return 0; \
24 }
25
26 customX(0)
27 customX(1)
28 customX(2)
29 customX(3)
30
31 std::vector<insn_desc_t> rocc_t::get_instructions()
32 {
33 std::vector<insn_desc_t> insns;
34 insns.push_back((insn_desc_t){0x0b, 0x7f, &::illegal_instruction, c0});
35 insns.push_back((insn_desc_t){0x2b, 0x7f, &::illegal_instruction, c1});
36 insns.push_back((insn_desc_t){0x5b, 0x7f, &::illegal_instruction, c2});
37 insns.push_back((insn_desc_t){0x7b, 0x7f, &::illegal_instruction, c3});
38 return insns;
39 }
40
41 std::vector<disasm_insn_t*> rocc_t::get_disasms()
42 {
43 std::vector<disasm_insn_t*> insns;
44 return insns;
45 }