-module cpu(
- input clk,
- input reset,
- output tty_write,
- output [7:0] tty_write_data,
- input tty_write_busy,
- input switch_2,
- input switch_3,
- output led_1,
- output led_3
- );
-
- parameter ram_size = 'h8000;
- parameter ram_start = 32'h1_0000;
- parameter reset_vector = ram_start;
- parameter mtvec = ram_start + 'h40;
-
- reg [31:0] registers[31:1];
-
- wire [31:2] memory_interface_fetch_address;
- wire [31:0] memory_interface_fetch_data;
- wire memory_interface_fetch_valid;
- wire [31:2] memory_interface_rw_address;
- wire [3:0] memory_interface_rw_byte_mask;
- wire memory_interface_rw_read_not_write;
- wire memory_interface_rw_active;
- wire [31:0] memory_interface_rw_data_in;
- wire [31:0] memory_interface_rw_data_out;
- wire memory_interface_rw_address_valid;
- wire memory_interface_rw_wait;
-
- cpu_memory_interface #(
- .ram_size(ram_size),
- .ram_start(ram_start)
- ) memory_interface(
- .clk(clk),
- .reset(reset),
- .fetch_address(memory_interface_fetch_address),
- .fetch_data(memory_interface_fetch_data),
- .fetch_valid(memory_interface_fetch_valid),
- .rw_address(memory_interface_rw_address),
- .rw_byte_mask(memory_interface_rw_byte_mask),
- .rw_read_not_write(memory_interface_rw_read_not_write),
- .rw_active(memory_interface_rw_active),
- .rw_data_in(memory_interface_rw_data_in),
- .rw_data_out(memory_interface_rw_data_out),
- .rw_address_valid(memory_interface_rw_address_valid),
- .rw_wait(memory_interface_rw_wait),
- .tty_write(tty_write),
- .tty_write_data(tty_write_data),
- .tty_write_busy(tty_write_busy),
- .switch_2(switch_2),
- .switch_3(switch_3),
- .led_1(led_1),
- .led_3(led_3)
- );
-
- wire `fetch_action fetch_action;
- wire [31:0] fetch_target_pc;
- wire [31:0] fetch_output_pc;
- wire [31:0] fetch_output_instruction;
- wire `fetch_output_state fetch_output_state;
-
- cpu_fetch_stage #(
- .reset_vector(reset_vector),
- .mtvec(mtvec)
- ) fetch_stage(
- .clk(clk),
- .reset(reset),
- .memory_interface_fetch_address(memory_interface_fetch_address),
- .memory_interface_fetch_data(memory_interface_fetch_data),
- .memory_interface_fetch_valid(memory_interface_fetch_valid),
- .fetch_action(fetch_action),
- .target_pc(fetch_target_pc),
- .output_pc(fetch_output_pc),
- .output_instruction(fetch_output_instruction),
- .output_state(fetch_output_state)
- );
-
- wire [6:0] decoder_funct7;
- wire [2:0] decoder_funct3;
- wire [4:0] decoder_rd;
- wire [4:0] decoder_rs1;
- wire [4:0] decoder_rs2;
- wire [31:0] decoder_immediate;
- wire [6:0] decoder_opcode;
- wire `decode_action decode_action;
-
- cpu_decoder decoder(
- .instruction(fetch_output_instruction),
- .funct7(decoder_funct7),
- .funct3(decoder_funct3),
- .rd(decoder_rd),
- .rs1(decoder_rs1),
- .rs2(decoder_rs2),
- .immediate(decoder_immediate),
- .opcode(decoder_opcode),
- .decode_action(decode_action));
-
- wire [31:0] register_rs1 = (decoder_rs1 == 0) ? 0 : registers[decoder_rs1];
- wire [31:0] register_rs2 = (decoder_rs2 == 0) ? 0 : registers[decoder_rs2];
-
- wire [31:0] load_store_address = decoder_immediate + register_rs1;
-
- wire [1:0] load_store_address_low_2 = decoder_immediate[1:0] + register_rs1[1:0];
-
- function get_load_store_misaligned(
- input [2:0] funct3,
- input [1:0] load_store_address_low_2
- );
- begin
- case(funct3[1:0])
- `funct3_sb:
- get_load_store_misaligned = 0;
- `funct3_sh:
- get_load_store_misaligned = load_store_address_low_2[0] != 0;
- `funct3_sw:
- get_load_store_misaligned = load_store_address_low_2[1:0] != 0;
- default:
- get_load_store_misaligned = 1'bX;
- endcase
- end
- endfunction
-
- wire load_store_misaligned = get_load_store_misaligned(decoder_funct3, load_store_address_low_2);
-
- assign memory_interface_rw_address = load_store_address[31:2];
-
- wire [3:0] unshifted_load_store_byte_mask = {decoder_funct3[1] ? 2'b11 : 2'b00, (decoder_funct3[1] | decoder_funct3[0]) ? 1'b1 : 1'b0, 1'b1};