load value

[rv32.git] / cpu.py

diff --git a/cpu.py b/cpu.py
index 20da63779889a993f2230f2ba72c5672b9c31bda..efe7270a937ece24e5642f6dcda05526410f5c6d 100644 (file)
--- a/cpu.py
+++ b/cpu.py
@@ -28,6 +28,7 @@
 
 from migen import *
 from migen.fhdl import verilog
+from migen.fhdl.structure import _Operator
 
 from riscvdefs import *
 from cpudefs import *
@@ -58,6 +59,13 @@ class CPU(Module):
                   "default": ls.eq(Constant(1))
                 })
 
+    def get_lsbm(self, decoder_funct3):
+        return Cat(Constant(1),
+                   Mux((decoder_funct3[1] | decoder_funct3[0]),
+                       Constant(1), Constant(0)),
+                   Mux((decoder_funct3[1]),
+                       Constant(0b11, 2), Constant(0, 2)))
+
     def __init__(self):
         #self.clk = ClockSignal()
         #self.reset = ResetSignal()
@@ -82,9 +90,6 @@ class CPU(Module):
             l.append(Signal(32, name="register%d" % i))
         registers = Array(l)
 
-        #self.sync += self.registers[0].eq(0)
-        #self.sync += self.registers[1].eq(0)
-
         mi = MemoryInterface()
 
         mii = Instance("cpu_memory_interface", name="memory_instance",
@@ -181,6 +186,47 @@ class CPU(Module):
                                      load_store_address_low_2)
         self.comb += lsa
 
+        # XXX rwaddr not 31:2 any more
+        self.comb += mi.rw_address.eq(load_store_address[2:])
+
+        unshifted_load_store_byte_mask = Signal(4)
+
+        self.comb += unshifted_load_store_byte_mask.eq(self.get_lsbm(
+                                                       decoder_funct3))
+
+        # XXX yuck.  this will cause migen simulation to fail
+        # (however conversion to verilog works)
+        self.comb += mi.rw_byte_mask.eq(
+                _Operator("<<", [unshifted_load_store_byte_mask,
+                                        load_store_address_low_2]))
+
+        # XXX not obvious
+        b3 = Mux(load_store_address_low_2[1],
+                 Mux(load_store_address_low_2[0], register_rs2[0:8],
+                                                  register_rs2[8:16]),
+                 Mux(load_store_address_low_2[0], register_rs2[16:24],
+                                                  register_rs2[24:32]))
+        b2 = Mux(load_store_address_low_2[1], register_rs2[0:8],
+                                              register_rs2[16:24])
+        b1 = Mux(load_store_address_low_2[0], register_rs2[0:8],
+                                              register_rs2[8:16])
+        b0 = register_rs2[0:8]
+
+        self.comb += mi.rw_data_in.eq(Cat(b0, b1, b2, b3))
+
+        # XXX not obvious
+        unmasked_loaded_value = Signal(32)
+
+        b0 = Mux(load_store_address_low_2[1],
+                 Mux(load_store_address_low_2[0], mi.rw_data_out[24:32],
+                                                  mi.rw_data_out[16:24]),
+                 Mux(load_store_address_low_2[0], mi.rw_data_out[15:8],
+                                                  mi.rw_data_out[0:8]))
+        b1 = Mux(load_store_address_low_2[1], mi.rw_data_out[24:31],
+                                              mi.rw_data_out[8:16])
+        b23 = mi.rw_data_out[16:32]
+
+        self.comb += unmasked_loaded_value.eq(Cat(b0, b1, b23))
 
 if __name__ == "__main__":
     example = CPU()
@@ -197,27 +243,6 @@ if __name__ == "__main__":
 
 """
 
-    assign memory_interface_rw_address = load_store_address[31:2];
-
-    wire [3:0] unshifted_load_store_byte_mask = {decoder_funct3[1] ? 2'b11 : 2'b00, (decoder_funct3[1] | decoder_funct3[0]) ? 1'b1 : 1'b0, 1'b1};
-
-    assign memory_interface_rw_byte_mask = unshifted_load_store_byte_mask << load_store_address_low_2;
-
-    assign memory_interface_rw_data_in[31:24] = load_store_address_low_2[1]
-                                                ? (load_store_address_low_2[0] ? register_rs2[7:0] : register_rs2[15:8])
-                                                : (load_store_address_low_2[0] ? register_rs2[23:16] : register_rs2[31:24]);
-    assign memory_interface_rw_data_in[23:16] = load_store_address_low_2[1] ? register_rs2[7:0] : register_rs2[23:16];
-    assign memory_interface_rw_data_in[15:8] = load_store_address_low_2[0] ? register_rs2[7:0] : register_rs2[15:8];
-    assign memory_interface_rw_data_in[7:0] = register_rs2[7:0];
-
-    wire [31:0] unmasked_loaded_value;
-
-    assign unmasked_loaded_value[7:0] = load_store_address_low_2[1]
-                                        ? (load_store_address_low_2[0] ? memory_interface_rw_data_out[31:24] : memory_interface_rw_data_out[23:16])
-                                        : (load_store_address_low_2[0] ? memory_interface_rw_data_out[15:8] : memory_interface_rw_data_out[7:0]);
-    assign unmasked_loaded_value[15:8] = load_store_address_low_2[1] ? memory_interface_rw_data_out[31:24] : memory_interface_rw_data_out[15:8];
-    assign unmasked_loaded_value[31:16] = memory_interface_rw_data_out[31:16];
-
     wire [31:0] loaded_value;
 
     assign loaded_value[7:0] = unmasked_loaded_value[7:0];