remove trap_handled, remove w_en

[rv32.git] / cpu_handle_trap.py

diff --git a/cpu_handle_trap.py b/cpu_handle_trap.py
index eaf3dafc441b9950d768a08bc9bf29fe2091eb28..c77be862b9893f5022ea87c2ddca9456495a9fdf 100644 (file)
--- a/cpu_handle_trap.py
+++ b/cpu_handle_trap.py
@@ -45,7 +45,6 @@ class CPUHandleTrap(Module):
         self.reset = ResetSignal()
 
         self.handle_trap = Signal()
-        self.trap_handled = Signal()
         self.ft_action = Signal(fetch_action)
         self.dc_action = Signal(decode_action)
         self.dc_immediate = Signal(32)
@@ -102,11 +101,7 @@ class CPUHandleTrap(Module):
 
         s.append(i)
 
-        self.sync += If(self.handle_trap,
-                        [s, self.trap_handled.eq(1)]
-                     ).Else(
-                        self.trap_handled.eq(0)
-                     )
+        self.sync += If(self.handle_trap, s)
 
 
 if __name__ == "__main__":
@@ -114,7 +109,6 @@ if __name__ == "__main__":
     print(verilog.convert(example,
          {
             example.handle_trap,
-            example.trap_handled,
             example.ft_action,
             example.dc_immediate,
             example.mcause,