#define AC_ACCESS_REGISTER None
-#define AC_ACCESS_REGISTER_PREHALT_OFFSET 23
-#define AC_ACCESS_REGISTER_PREHALT_LENGTH 1
-#define AC_ACCESS_REGISTER_PREHALT (0x1 << AC_ACCESS_REGISTER_PREHALT_OFFSET)
-#define AC_ACCESS_REGISTER_POSTRESUME_OFFSET 22
-#define AC_ACCESS_REGISTER_POSTRESUME_LENGTH 1
-#define AC_ACCESS_REGISTER_POSTRESUME (0x1 << AC_ACCESS_REGISTER_POSTRESUME_OFFSET)
#define AC_ACCESS_REGISTER_SIZE_OFFSET 19
#define AC_ACCESS_REGISTER_SIZE_LENGTH 3
#define AC_ACCESS_REGISTER_SIZE (0x7 << AC_ACCESS_REGISTER_SIZE_OFFSET)
#define AC_ACCESS_REGISTER_REGNO_OFFSET 0
#define AC_ACCESS_REGISTER_REGNO_LENGTH 16
#define AC_ACCESS_REGISTER_REGNO (0xffff << AC_ACCESS_REGISTER_REGNO_OFFSET)
+#define AC_QUICK_ACCESS None
+#define AC_QUICK_ACCESS_1_OFFSET 24
+#define AC_QUICK_ACCESS_1_LENGTH 8
+#define AC_QUICK_ACCESS_1 (0xff << AC_QUICK_ACCESS_1_OFFSET)
#define CSR_DCSR 0x7b0
#define CSR_DCSR_XDEBUGVER_OFFSET 30
#define CSR_DCSR_XDEBUGVER_LENGTH 2
#define DMI_DMCONTROL_VERSION_OFFSET 0
#define DMI_DMCONTROL_VERSION_LENGTH 4
#define DMI_DMCONTROL_VERSION (0xf << DMI_DMCONTROL_VERSION_OFFSET)
+#define DMI_HARTINFO 0x01
+#define DMI_HARTINFO_DATAACCESS_OFFSET 16
+#define DMI_HARTINFO_DATAACCESS_LENGTH 1
+#define DMI_HARTINFO_DATAACCESS (0x1 << DMI_HARTINFO_DATAACCESS_OFFSET)
+#define DMI_HARTINFO_DATASIZE_OFFSET 12
+#define DMI_HARTINFO_DATASIZE_LENGTH 4
+#define DMI_HARTINFO_DATASIZE (0xf << DMI_HARTINFO_DATASIZE_OFFSET)
+#define DMI_HARTINFO_DATAADDR_OFFSET 0
+#define DMI_HARTINFO_DATAADDR_LENGTH 12
+#define DMI_HARTINFO_DATAADDR (0xfff << DMI_HARTINFO_DATAADDR_OFFSET)
#define DMI_HALTSUM 0x02
#define DMI_HALTSUM_HALT1023_992_OFFSET 31
#define DMI_HALTSUM_HALT1023_992_LENGTH 1
#define DMI_SBDATA3_DATA_OFFSET 0
#define DMI_SBDATA3_DATA_LENGTH 32
#define DMI_SBDATA3_DATA (0xffffffff << DMI_SBDATA3_DATA_OFFSET)
-#define DMI_ABSTRACTCS 0x0b
+#define DMI_AUTHDATA0 0x0b
+#define DMI_AUTHDATA0_DATA_OFFSET 0
+#define DMI_AUTHDATA0_DATA_LENGTH 32
+#define DMI_AUTHDATA0_DATA (0xffffffff << DMI_AUTHDATA0_DATA_OFFSET)
+#define DMI_AUTHDATA1 0x0c
+#define DMI_AUTHDATA1_DATA_OFFSET 0
+#define DMI_AUTHDATA1_DATA_LENGTH 32
+#define DMI_AUTHDATA1_DATA (0xffffffff << DMI_AUTHDATA1_DATA_OFFSET)
+#define DMI_ABSTRACTCS 0x0e
#define DMI_ABSTRACTCS_AUTOEXEC7_OFFSET 15
#define DMI_ABSTRACTCS_AUTOEXEC7_LENGTH 1
#define DMI_ABSTRACTCS_AUTOEXEC7 (0x1 << DMI_ABSTRACTCS_AUTOEXEC7_OFFSET)
#define DMI_ABSTRACTCS_DATACOUNT_OFFSET 0
#define DMI_ABSTRACTCS_DATACOUNT_LENGTH 4
#define DMI_ABSTRACTCS_DATACOUNT (0xf << DMI_ABSTRACTCS_DATACOUNT_OFFSET)
-#define DMI_COMMAND 0x0c
+#define DMI_COMMAND 0x0f
#define DMI_COMMAND_COMMAND_OFFSET 0
#define DMI_COMMAND_COMMAND_LENGTH 32
#define DMI_COMMAND_COMMAND (0xffffffff << DMI_COMMAND_COMMAND_OFFSET)
-#define DMI_DATA0 0x0d
+#define DMI_DATA0 0x10
#define DMI_DATA0_DATA_OFFSET 0
#define DMI_DATA0_DATA_LENGTH 32
#define DMI_DATA0_DATA (0xffffffff << DMI_DATA0_DATA_OFFSET)
-#define DMI_DATA1 0x0e
-#define DMI_DATA2 0x0f
-#define DMI_DATA3 0x10
-#define DMI_DATA4 0x11
-#define DMI_DATA5 0x12
-#define DMI_DATA6 0x13
-#define DMI_DATA7 0x14
-#define DMI_ACCESSCS 0x15
-#define DMI_ACCESSCS_PROGSIZE_OFFSET 0
-#define DMI_ACCESSCS_PROGSIZE_LENGTH 4
-#define DMI_ACCESSCS_PROGSIZE (0xf << DMI_ACCESSCS_PROGSIZE_OFFSET)
-#define DMI_IBUF0 0x18
-#define DMI_IBUF0_DATA_OFFSET 0
-#define DMI_IBUF0_DATA_LENGTH 32
-#define DMI_IBUF0_DATA (0xffffffff << DMI_IBUF0_DATA_OFFSET)
-#define DMI_IBUF1 0x19
-#define DMI_IBUF2 0x1a
-#define DMI_IBUF3 0x1b
-#define DMI_IBUF4 0x1c
-#define DMI_IBUF5 0x1d
-#define DMI_IBUF6 0x1e
-#define DMI_IBUF7 0x1f
-#define DMI_AUTHDATA0 0x20
-#define DMI_AUTHDATA0_DATA_OFFSET 0
-#define DMI_AUTHDATA0_DATA_LENGTH 32
-#define DMI_AUTHDATA0_DATA (0xffffffff << DMI_AUTHDATA0_DATA_OFFSET)
-#define DMI_AUTHDATA1 0x21
-#define DMI_AUTHDATA1_DATA_OFFSET 0
-#define DMI_AUTHDATA1_DATA_LENGTH 32
-#define DMI_AUTHDATA1_DATA (0xffffffff << DMI_AUTHDATA1_DATA_OFFSET)
-#define DMI_SERDATA 0x22
+#define DMI_DATA1 0x11
+#define DMI_DATA2 0x12
+#define DMI_DATA3 0x13
+#define DMI_DATA4 0x14
+#define DMI_DATA5 0x15
+#define DMI_DATA6 0x16
+#define DMI_DATA7 0x17
+#define DMI_DATA8 0x18
+#define DMI_DATA9 0x19
+#define DMI_DATA10 0x1a
+#define DMI_DATA11 0x1b
+#define DMI_SERDATA 0x1c
#define DMI_SERDATA_DATA_OFFSET 0
#define DMI_SERDATA_DATA_LENGTH 32
#define DMI_SERDATA_DATA (0xffffffff << DMI_SERDATA_DATA_OFFSET)
-#define DMI_SERSTATUS 0x23
+#define DMI_SERSTATUS 0x1d
#define DMI_SERSTATUS_SERIALCOUNT_OFFSET 28
#define DMI_SERSTATUS_SERIALCOUNT_LENGTH 4
#define DMI_SERSTATUS_SERIALCOUNT (0xf << DMI_SERSTATUS_SERIALCOUNT_OFFSET)
#define DMI_SERSTATUS_FULL_OVERFLOW0_OFFSET 0
#define DMI_SERSTATUS_FULL_OVERFLOW0_LENGTH 1
#define DMI_SERSTATUS_FULL_OVERFLOW0 (0x1 << DMI_SERSTATUS_FULL_OVERFLOW0_OFFSET)
+#define DMI_ACCESSCS 0x1f
+#define DMI_ACCESSCS_PROGSIZE_OFFSET 0
+#define DMI_ACCESSCS_PROGSIZE_LENGTH 4
+#define DMI_ACCESSCS_PROGSIZE (0xf << DMI_ACCESSCS_PROGSIZE_OFFSET)
+#define DMI_IBUF0 0x20
+#define DMI_IBUF0_DATA_OFFSET 0
+#define DMI_IBUF0_DATA_LENGTH 32
+#define DMI_IBUF0_DATA (0xffffffff << DMI_IBUF0_DATA_OFFSET)
+#define DMI_IBUF1 0x21
+#define DMI_IBUF2 0x22
+#define DMI_IBUF3 0x23
+#define DMI_IBUF4 0x24
+#define DMI_IBUF5 0x25
+#define DMI_IBUF6 0x26
+#define DMI_IBUF7 0x27
+#define DMI_IBUF8 0x28
+#define DMI_IBUF9 0x29
+#define DMI_IBUF10 0x2a
+#define DMI_IBUF11 0x2b
#define SERINFO 0x110
#define SERINFO_SERIAL7_OFFSET 7
#define SERINFO_SERIAL7_LENGTH 1
#define DTM_INIT__SETUP__CLAMP 0x0c
#define DTM_INIT__RUN 0x0d
#define DTM_DTMCONTROL 0x10
-#define DTM_DTMCONTROL_DBUSRESET_OFFSET 16
-#define DTM_DTMCONTROL_DBUSRESET_LENGTH 1
-#define DTM_DTMCONTROL_DBUSRESET (0x1 << DTM_DTMCONTROL_DBUSRESET_OFFSET)
+#define DTM_DTMCONTROL_DMIRESET_OFFSET 16
+#define DTM_DTMCONTROL_DMIRESET_LENGTH 1
+#define DTM_DTMCONTROL_DMIRESET (0x1 << DTM_DTMCONTROL_DMIRESET_OFFSET)
#define DTM_DTMCONTROL_IDLE_OFFSET 12
#define DTM_DTMCONTROL_IDLE_LENGTH 3
#define DTM_DTMCONTROL_IDLE (0x7 << DTM_DTMCONTROL_IDLE_OFFSET)
-#define DTM_DTMCONTROL_DBUSSTAT_OFFSET 10
-#define DTM_DTMCONTROL_DBUSSTAT_LENGTH 2
-#define DTM_DTMCONTROL_DBUSSTAT (0x3 << DTM_DTMCONTROL_DBUSSTAT_OFFSET)
+#define DTM_DTMCONTROL_DMISTAT_OFFSET 10
+#define DTM_DTMCONTROL_DMISTAT_LENGTH 2
+#define DTM_DTMCONTROL_DMISTAT (0x3 << DTM_DTMCONTROL_DMISTAT_OFFSET)
#define DTM_DTMCONTROL_ABITS_OFFSET 4
#define DTM_DTMCONTROL_ABITS_LENGTH 6
#define DTM_DTMCONTROL_ABITS (0x3f << DTM_DTMCONTROL_ABITS_OFFSET)
#define DTM_DTMCONTROL_VERSION_OFFSET 0
#define DTM_DTMCONTROL_VERSION_LENGTH 4
#define DTM_DTMCONTROL_VERSION (0xf << DTM_DTMCONTROL_VERSION_OFFSET)
-#define DTM_DBUS 0x11
-#define DTM_DBUS_ADDRESS_OFFSET 34
-#define DTM_DBUS_ADDRESS_LENGTH abits
-#define DTM_DBUS_ADDRESS (((1L<<abits)-1) << DTM_DBUS_ADDRESS_OFFSET)
-#define DTM_DBUS_DATA_OFFSET 2
-#define DTM_DBUS_DATA_LENGTH 32
-#define DTM_DBUS_DATA (0xffffffff << DTM_DBUS_DATA_OFFSET)
-#define DTM_DBUS_OP_OFFSET 0
-#define DTM_DBUS_OP_LENGTH 2
-#define DTM_DBUS_OP (0x3 << DTM_DBUS_OP_OFFSET)
+#define DTM_DMI 0x11
+#define DTM_DMI_ADDRESS_OFFSET 34
+#define DTM_DMI_ADDRESS_LENGTH abits
+#define DTM_DMI_ADDRESS (((1L<<abits)-1) << DTM_DMI_ADDRESS_OFFSET)
+#define DTM_DMI_DATA_OFFSET 2
+#define DTM_DMI_DATA_LENGTH 32
+#define DTM_DMI_DATA (0xffffffff << DTM_DMI_DATA_OFFSET)
+#define DTM_DMI_OP_OFFSET 0
+#define DTM_DMI_OP_LENGTH 2
+#define DTM_DMI_OP (0x3 << DTM_DMI_OP_OFFSET)
#define SHORTNAME 0x123
#define SHORTNAME_FIELD_OFFSET 0
#define SHORTNAME_FIELD_LENGTH 8
projects / riscv-isa-sim.git / blobdiff