dbus -> dmi

diff --git a/riscv/debug_defines.h b/riscv/debug_defines.h
index f9fdaa0cfae58a9fdb593ce2ccf89b6f4296dc97..5666f46386711df28df01e0ebf1af15a5561a579 100644 (file)
--- a/riscv/debug_defines.h
+++ b/riscv/debug_defines.h
@@ -572,31 +572,31 @@
 #define DTM_INIT__SETUP__CLAMP              0x0c
 #define DTM_INIT__RUN                       0x0d
 #define DTM_DTMCONTROL                      0x10
-#define DTM_DTMCONTROL_DBUSRESET_OFFSET     16
-#define DTM_DTMCONTROL_DBUSRESET_LENGTH     1
-#define DTM_DTMCONTROL_DBUSRESET            (0x1 << DTM_DTMCONTROL_DBUSRESET_OFFSET)
+#define DTM_DTMCONTROL_DMIRESET_OFFSET      16
+#define DTM_DTMCONTROL_DMIRESET_LENGTH      1
+#define DTM_DTMCONTROL_DMIRESET             (0x1 << DTM_DTMCONTROL_DMIRESET_OFFSET)
 #define DTM_DTMCONTROL_IDLE_OFFSET          12
 #define DTM_DTMCONTROL_IDLE_LENGTH          3
 #define DTM_DTMCONTROL_IDLE                 (0x7 << DTM_DTMCONTROL_IDLE_OFFSET)
-#define DTM_DTMCONTROL_DBUSSTAT_OFFSET      10
-#define DTM_DTMCONTROL_DBUSSTAT_LENGTH      2
-#define DTM_DTMCONTROL_DBUSSTAT             (0x3 << DTM_DTMCONTROL_DBUSSTAT_OFFSET)
+#define DTM_DTMCONTROL_DMISTAT_OFFSET       10
+#define DTM_DTMCONTROL_DMISTAT_LENGTH       2
+#define DTM_DTMCONTROL_DMISTAT              (0x3 << DTM_DTMCONTROL_DMISTAT_OFFSET)
 #define DTM_DTMCONTROL_ABITS_OFFSET         4
 #define DTM_DTMCONTROL_ABITS_LENGTH         6
 #define DTM_DTMCONTROL_ABITS                (0x3f << DTM_DTMCONTROL_ABITS_OFFSET)
 #define DTM_DTMCONTROL_VERSION_OFFSET       0
 #define DTM_DTMCONTROL_VERSION_LENGTH       4
 #define DTM_DTMCONTROL_VERSION              (0xf << DTM_DTMCONTROL_VERSION_OFFSET)
-#define DTM_DBUS                            0x11
-#define DTM_DBUS_ADDRESS_OFFSET             34
-#define DTM_DBUS_ADDRESS_LENGTH             abits
-#define DTM_DBUS_ADDRESS                    (((1L<<abits)-1) << DTM_DBUS_ADDRESS_OFFSET)
-#define DTM_DBUS_DATA_OFFSET                2
-#define DTM_DBUS_DATA_LENGTH                32
-#define DTM_DBUS_DATA                       (0xffffffff << DTM_DBUS_DATA_OFFSET)
-#define DTM_DBUS_OP_OFFSET                  0
-#define DTM_DBUS_OP_LENGTH                  2
-#define DTM_DBUS_OP                         (0x3 << DTM_DBUS_OP_OFFSET)
+#define DTM_DMI                             0x11
+#define DTM_DMI_ADDRESS_OFFSET              34
+#define DTM_DMI_ADDRESS_LENGTH              abits
+#define DTM_DMI_ADDRESS                     (((1L<<abits)-1) << DTM_DMI_ADDRESS_OFFSET)
+#define DTM_DMI_DATA_OFFSET                 2
+#define DTM_DMI_DATA_LENGTH                 32
+#define DTM_DMI_DATA                        (0xffffffff << DTM_DMI_DATA_OFFSET)
+#define DTM_DMI_OP_OFFSET                   0
+#define DTM_DMI_OP_LENGTH                   2
+#define DTM_DMI_OP                          (0x3 << DTM_DMI_OP_OFFSET)
 #define SHORTNAME                           0x123
 #define SHORTNAME_FIELD_OFFSET              0
 #define SHORTNAME_FIELD_LENGTH              8

diff --git a/riscv/debug_module.cc b/riscv/debug_module.cc
index 1a165e437965a8015e02c6fb1fa33fbccab53905..551db17b454a7dbcb57708ae7be2661db789478a 100644 (file)
--- a/riscv/debug_module.cc
+++ b/riscv/debug_module.cc
@@ -362,7 +362,7 @@ bool debug_module_t::dmi_write(unsigned address, uint32_t value)
         if (get_field(value, DMI_ABSTRACTCS_CMDERR) == abstractcs.CMDERR_NONE) {
           abstractcs.cmderr = abstractcs.CMDERR_NONE;
         }
-        break;
+        return true;
     }
   }
   return false;

diff --git a/riscv/jtag_dtm.cc b/riscv/jtag_dtm.cc
index 2ce194c2c4e13096bd229095b966f4629598f961..84f13f8d7bd9de96fa8dc5fa6d2dd8e4fd7f958f 100644 (file)
--- a/riscv/jtag_dtm.cc
+++ b/riscv/jtag_dtm.cc
@@ -23,25 +23,25 @@ enum {
 #define DTMCONTROL_IDLE         (7<<12)
 #define DTMCONTROL_DBUSRESET    (1<<16)
 
-#define DBUS_OP                 3
-#define DBUS_DATA               (0xffffffffL<<2)
-#define DBUS_ADDRESS            ((1L<<(abits+34)) - (1L<<34))
+#define DMI_OP                 3
+#define DMI_DATA               (0xffffffffL<<2)
+#define DMI_ADDRESS            ((1L<<(abits+34)) - (1L<<34))
 
-#define DBUS_OP_STATUS_SUCCESS 0
-#define DBUS_OP_STATUS_RESERVED        1
-#define DBUS_OP_STATUS_FAILED  2
-#define DBUS_OP_STATUS_BUSY    3
+#define DMI_OP_STATUS_SUCCESS  0
+#define DMI_OP_STATUS_RESERVED 1
+#define DMI_OP_STATUS_FAILED   2
+#define DMI_OP_STATUS_BUSY     3
 
-#define DBUS_OP_NOP            0
-#define DBUS_OP_READ           1
-#define DBUS_OP_READ_WRITE     2
-#define DBUS_OP_RESERVED       3
+#define DMI_OP_NOP             0
+#define DMI_OP_READ            1
+#define DMI_OP_READ_WRITE      2
+#define DMI_OP_RESERVED        3
 
 jtag_dtm_t::jtag_dtm_t(debug_module_t *dm) :
   dm(dm),
   _tck(false), _tms(false), _tdi(false), _tdo(false),
   dtmcontrol((abits << DTM_DTMCONTROL_ABITS_OFFSET) | 1),
-  dbus(DBUS_OP_STATUS_FAILED << DTM_DBUS_OP_OFFSET),
+  dmi(DMI_OP_STATUS_FAILED << DTM_DMI_OP_OFFSET),
   state(TEST_LOGIC_RESET)
 {
 }
@@ -134,7 +134,7 @@ void jtag_dtm_t::capture_dr()
       dr_length = 32;
       break;
     case IR_DBUS:
-      dr = dbus;
+      dr = dmi;
       dr_length = abits + 34;
       break;
     default:
@@ -152,31 +152,31 @@ void jtag_dtm_t::update_dr()
   switch (ir) {
     case IR_DBUS:
       {
-        unsigned op = get_field(dr, DBUS_OP);
-        uint32_t data = get_field(dr, DBUS_DATA);
-        unsigned address = get_field(dr, DBUS_ADDRESS);
+        unsigned op = get_field(dr, DMI_OP);
+        uint32_t data = get_field(dr, DMI_DATA);
+        unsigned address = get_field(dr, DMI_ADDRESS);
 
-        dbus = dr;
+        dmi = dr;
 
         bool success = true;
-        if (op == DBUS_OP_READ || op == DBUS_OP_READ_WRITE) {
+        if (op == DMI_OP_READ || op == DMI_OP_READ_WRITE) {
           uint32_t value;
           if (dm->dmi_read(address, &value)) {
-            dbus = set_field(dbus, DBUS_DATA, value);
+            dmi = set_field(dmi, DMI_DATA, value);
           } else {
             success = false;
           }
         }
-        if (success && op == DBUS_OP_READ_WRITE) {
+        if (success && op == DMI_OP_READ_WRITE) {
           success = dm->dmi_write(address, data);
         }
 
         if (success) {
-          dbus = set_field(dbus, DBUS_OP, DBUS_OP_STATUS_SUCCESS);
+          dmi = set_field(dmi, DMI_OP, DMI_OP_STATUS_SUCCESS);
         } else {
-          dbus = set_field(dbus, DBUS_OP, DBUS_OP_STATUS_FAILED);
+          dmi = set_field(dmi, DMI_OP, DMI_OP_STATUS_FAILED);
         }
-        D(fprintf(stderr, "dbus=0x%lx\n", dbus));
+        D(fprintf(stderr, "dmi=0x%lx\n", dmi));
       }
       break;
   }

diff --git a/riscv/jtag_dtm.h b/riscv/jtag_dtm.h
index 6d89c042aeeecd51173c8045dd63ab7db9158174..97ce52172692ccd7a0f476708c21c0fc1f035d24 100644 (file)
--- a/riscv/jtag_dtm.h
+++ b/riscv/jtag_dtm.h
@@ -48,7 +48,7 @@ class jtag_dtm_t
     // constructor.
     const unsigned abits = 6;
     uint32_t dtmcontrol;
-    uint64_t dbus;
+    uint64_t dmi;
 
     jtag_state_t state;