Have ndmreset reset the processor

[riscv-isa-sim.git] / riscv / debug_module.cc

diff --git a/riscv/debug_module.cc b/riscv/debug_module.cc
index 62671f67a25c8cc6b343e109b0ea9f4ec3ce1f0b..5f66ebed0a1843d07ac038c83baf9a5172e37ba7 100644 (file)
--- a/riscv/debug_module.cc
+++ b/riscv/debug_module.cc
@@ -126,7 +126,9 @@ bool debug_module_t::store(reg_t addr, size_t len, const uint8_t* bytes)
   }
   
   if (addr >= debug_progbuf_start && ((addr + len) <= (debug_progbuf_start + sizeof(program_buffer)))) {
+    fprintf(stderr, "Successful write to program buffer %d bytes at %x\n", (int) len, (int) addr);
     memcpy(program_buffer + addr - debug_progbuf_start, bytes, len);
+    
     return true;
   }
 
@@ -213,7 +215,7 @@ bool debug_module_t::dmi_read(unsigned address, uint32_t *value)
       perform_abstract_command();
     }
   } else if (address >= DMI_PROGBUF0 && address < DMI_PROGBUF0 + progsize) {
-    unsigned i = address = DMI_PROGBUF0;
+    unsigned i = address - DMI_PROGBUF0;
     result = read32(program_buffer, i);
     if ((abstractauto.autoexecprogbuf >> i) & 1) {
       perform_abstract_command();
@@ -435,6 +437,9 @@ bool debug_module_t::dmi_write(unsigned address, uint32_t value)
               debug_rom_flags[dmcontrol.hartsel] |= (1 << DEBUG_ROM_FLAG_RESUME);
               resumeack[dmcontrol.hartsel] = false;
             }
+           if (dmcontrol.ndmreset) {
+             proc->reset();
+           }
           }
         }
         return true;