[xcc,sim,opcodes] added more RVC instructions

[riscv-isa-sim.git] / riscv / decode.h

diff --git a/riscv/decode.h b/riscv/decode.h
index f411c10bec0468b14e0312fc099e67a42c24ed34..63e71cd98193354f735179620861c5b2c3705ded 100644 (file)
--- a/riscv/decode.h
+++ b/riscv/decode.h
@@ -210,21 +210,27 @@ private:
 
 #define INSN_IS_RVC(x) (((x) & 0x3) < 0x3)
 
-#define CRD do_writeback(XPR, (insn.bits >> 5) & 0x1f)
+#define CRD_REGNUM ((insn.bits >> 5) & 0x1f)
+#define CRD do_writeback(XPR, CRD_REGNUM)
 #define CRS1 XPR[(insn.bits >> 10) & 0x1f]
 #define CRS2 XPR[(insn.bits >> 5) & 0x1f]
 #define CIMM6 ((int32_t)((insn.bits >> 10) & 0x3f) << 26 >> 26)
-#define CIMM5 ((int32_t)((insn.bits >> 5) & 0x1f) << 27 >> 27)
+#define CIMM5U ((insn.bits >> 5) & 0x1f)
+#define CIMM5 ((int32_t)CIMM5U << 27 >> 27)
 #define CIMM10 ((int32_t)((insn.bits >> 5) & 0x3ff) << 22 >> 22)
 #define CBRANCH_TARGET (pc + (CIMM5 << BRANCH_ALIGN_BITS))
 #define CJUMP_TARGET (pc + (CIMM10 << JUMP_ALIGN_BITS))
 
 static const int rvc_rs1_regmap[8] = { 20, 21, 2, 3, 4, 5, 6, 7 };
 #define rvc_rd_regmap rvc_rs1_regmap
+#define rvc_rs2b_regmap rvc_rs1_regmap
 static const int rvc_rs2_regmap[8] = { 20, 21, 2, 3, 4, 5, 6, 0 };
-#define CRDS do_writeback(XPR, rvc_rd_regmap[(insn.bits >> 13) & 0x7])
+#define CRDS XPR[rvc_rd_regmap[(insn.bits >> 13) & 0x7]]
+#define FCRDS FPR[rvc_rd_regmap[(insn.bits >> 13) & 0x7]]
 #define CRS1S XPR[rvc_rs1_regmap[(insn.bits >> 10) & 0x7]]
 #define CRS2S XPR[rvc_rs2_regmap[(insn.bits >> 13) & 0x7]]
+#define CRS2BS XPR[rvc_rs2b_regmap[(insn.bits >> 5) & 0x7]]
+#define FCRS2S FPR[rvc_rs2_regmap[(insn.bits >> 13) & 0x7]]
 
 // vector stuff
 #define VL vl