Generate instruction decoder dynamically

[riscv-isa-sim.git] / riscv / disasm.cc

diff --git a/riscv/disasm.cc b/riscv/disasm.cc
index ca3b3dd7b610335c0ad55f006a176130bc670dd1..57f43d7f52f37c9e8ddaeb32e918ec7b6092368d 100644 (file)
--- a/riscv/disasm.cc
+++ b/riscv/disasm.cc
@@ -406,8 +406,8 @@ disassembler::disassembler()
   uint32_t match_rs1_ra = dummy.bits;
 
   #define DECLARE_INSN(code, match, mask) \
-   const uint32_t __attribute__((unused)) match_##code = match; \
-   const uint32_t __attribute__((unused)) mask_##code = mask;
+   const uint32_t match_##code = match; \
+   const uint32_t mask_##code = mask;
   #include "opcodes.h"
   #undef DECLARE_INSN