Change DCSR bits to match spec.

[riscv-isa-sim.git] / riscv / encoding.h

diff --git a/riscv/encoding.h b/riscv/encoding.h
index e3371af9a77126b90bb93dc6598372f00700c58d..0f1926a402e46eae5f62efd5441255f4a5b9c3d5 100644 (file)
--- a/riscv/encoding.h
+++ b/riscv/encoding.h
@@ -33,21 +33,21 @@
 #define SSTATUS32_SD        0x80000000
 #define SSTATUS64_SD        0x8000000000000000
 
-#define DCSR_XDEBUGVER      (3<<29)
-#define DCSR_HWBPCOUNT      (0xfff<<17)
-#define DCSR_PRV            (3<<14)
-#define DCSR_NDRESET        (1<<13)
-#define DCSR_FULLRESET      (1<<12)
-#define DCSR_STEP           (1<<11)
-#define DCSR_DEBUGINT       (1<<10)
-#define DCSR_STOPCYCLE      (1<<9)
-#define DCSR_STOPTIME       (1<<8)
-#define DCSR_EBREAKM        (1<<7)
-#define DCSR_EBREAKH        (1<<6)
-#define DCSR_EBREAKS        (1<<5)
-#define DCSR_EBREAKU        (1<<4)
+#define DCSR_XDEBUGVER      (3<<30)
+#define DCSR_NDRESET        (1<<29)
+#define DCSR_FULLRESET      (1<<28)
+#define DCSR_HWBPCOUNT      (0xfff<<16)
+#define DCSR_EBREAKM        (1<<15)
+#define DCSR_EBREAKH        (1<<14)
+#define DCSR_EBREAKS        (1<<13)
+#define DCSR_EBREAKU        (1<<12)
+#define DCSR_STOPCYCLE      (1<<10)
+#define DCSR_STOPTIME       (1<<9)
+#define DCSR_CAUSE          (7<<6)
+#define DCSR_DEBUGINT       (1<<5)
 #define DCSR_HALT           (1<<3)
-#define DCSR_CAUSE          7
+#define DCSR_STEP           (1<<2)
+#define DCSR_PRV            (3<<0)
 
 #define DCSR_CAUSE_NONE     0
 #define DCSR_CAUSE_SWBP     1