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[riscv-isa-sim.git]
/
riscv
/
execute.cc
diff --git
a/riscv/execute.cc
b/riscv/execute.cc
index ae4c9597a1bd00af5b9ecfd992c470c807659d66..a1c22292a410774a9ae06a11f66c0e16dff9bcd6 100644
(file)
--- a/
riscv/execute.cc
+++ b/
riscv/execute.cc
@@
-63,7
+63,7
@@
void processor_t::step(size_t n)
if (state.dcsr.cause != DCSR_CAUSE_NONE) {
// In Debug Mode, just do 10 steps at a time. Otherwise we're going to be
// spinning the rest of the time anyway.
- n = std::m
ax
(n, (size_t) 10);
+ n = std::m
in
(n, (size_t) 10);
}
while (n > 0) {