[opcodes, sim, xcc] made *w insns illegal in RV32

[riscv-isa-sim.git] / riscv / execute.h

diff --git a/riscv/execute.h b/riscv/execute.h
index ddc7b4271b094b1e03ab8eeb90bc591c36b98577..b8e396ad7312c4ca9be12d5fcb2ce5918de86433 100644 (file)
--- a/riscv/execute.h
+++ b/riscv/execute.h
@@ -768,11 +768,6 @@ switch((insn.bits >> 0x0) & 0x7f)
           #include "insns/divuw.h"
           break;
         }
-        if((insn.bits & 0x1ffff) == 0xcf7)
-        {
-          #include "insns/mulhuw.h"
-          break;
-        }
         if((insn.bits & 0x1ffff) == 0xf7)
         {
           #include "insns/mulw.h"
@@ -783,11 +778,6 @@ switch((insn.bits >> 0x0) & 0x7f)
           #include "insns/remw.h"
           break;
         }
-        if((insn.bits & 0x1ffff) == 0x8f7)
-        {
-          #include "insns/mulhw.h"
-          break;
-        }
         if((insn.bits & 0x1ffff) == 0x10f7)
         {
           #include "insns/divw.h"