[xcc,sim,opcodes] more rvc instructions and bug fixes

[riscv-isa-sim.git] / riscv / insns / c_addi.h

diff --git a/riscv/insns/c_addi.h b/riscv/insns/c_addi.h
index 2694a0acc59ef33bacb00d1c44e27b58135c2f14..4a5a0af20df78c3c35cf892c6487b9131356c6cf 100644 (file)
--- a/riscv/insns/c_addi.h
+++ b/riscv/insns/c_addi.h
@@ -1,2 +1,2 @@
 require_rvc;
-CRD = sext_xprlen(CRD + SIMM);
+CRD = sext_xprlen(CRS2 + CIMM6);