[opcodes, sim, xcc] made *w insns illegal in RV32

[riscv-isa-sim.git] / riscv / insns / divw.h

diff --git a/riscv/insns/divw.h b/riscv/insns/divw.h
index bfc982a7a50329ad7eab76a3395cc8a34f94eb0f..9c732b51247106d9903e1815f0a879f63f80d486 100644 (file)
--- a/riscv/insns/divw.h
+++ b/riscv/insns/divw.h
@@ -1,4 +1,7 @@
-if(int32_t(RS2) == 0 || (int32_t(RS1) == INT32_MIN && int32_t(RS2) == -1))
-  RD = sext32(int32_t(RS1) < 0 ? INT32_MIN : INT32_MAX);
+require_xpr64;
+// INT64_MIN/-1 corner case shouldn't occur in correct code, since
+// INT64_MIN is not a proper 32-bit signed value
+if(RS2 == 0 || (sreg_t(RS1) == INT64_MIN && sreg_t(RS2) == -1))
+  RD = sext32(sreg_t(RS1) < 0 ? INT32_MIN : INT32_MAX);
 else
-  RD = sext32(int32_t(RS1)/int32_t(RS2));
+  RD = sext32(sreg_t(RS1) / sreg_t(RS2));