[sim] add vt stuff

[riscv-isa-sim.git] / riscv / insns / lw_v.h

diff --git a/riscv/insns/lw_v.h b/riscv/insns/lw_v.h
index e69de29bb2d1d6434b8b29ae775ad8c2e48c5391..980a164e9c31a66ffb8c371f5262bc9ab005facf 100644 (file)
--- a/riscv/insns/lw_v.h
+++ b/riscv/insns/lw_v.h
@@ -0,0 +1 @@
+VEC_LOAD(RD, load_int32, 4);