[sim] add vt stuff

diff --git a/riscv/decode.h b/riscv/decode.h
index bb1f605c0fc31a933e299bfb3ffc4b7383574c13..c2702a602e76d5923668cf866f4d151eec402c62 100644 (file)
--- a/riscv/decode.h
+++ b/riscv/decode.h
@@ -207,4 +207,49 @@ private:
 #define CRD do_writeback(XPR,(insn.bits >> 5) & 0x1f)
 #define CIMM6 ((int32_t)((insn.bits >> 10) & 0x3f) << 26 >> 26)
 
+// vector stuff
+#define VL vl
+
+#define UT_RS1(idx) uts[idx]->XPR[insn.rtype.rs1]
+#define UT_RS2(idx) uts[idx]->XPR[insn.rtype.rs2]
+#define UT_RD(idx) do_writeback(uts[idx]->XPR,insn.rtype.rd)
+#define UT_RA(idx) do_writeback(uts[idx]->XPR,1)
+#define UT_FRS1(idx) uts[idx]->FPR[insn.ftype.rs1]
+#define UT_FRS2(idx) uts[idx]->FPR[insn.ftype.rs2]
+#define UT_FRS3(idx) uts[idx]->FPR[insn.ftype.rs3]
+#define UT_FRD(idx) uts[idx]->FPR[insn.ftype.rd]
+#define UT_RM(idx) ((insn.ftype.rm != 7) ? insn.ftype.rm : \
+              ((uts[idx]->fsr & FSR_RD) >> FSR_RD_SHIFT))
+
+#define UT_LOOP_START for (int i=0;i<VL; i++) {
+#define UT_LOOP_END }
+#define UT_LOOP_RS1 UT_RS1(i)
+#define UT_LOOP_RS2 UT_RS2(i)
+#define UT_LOOP_RD UT_RD(i)
+#define UT_LOOP_RA UT_RA(i)
+#define UT_LOOP_FRS1 UT_FRS1(i)
+#define UT_LOOP_FRS2 UT_FRS2(i)
+#define UT_LOOP_FRS3 UT_FRS3(i)
+#define UT_LOOP_FRD UT_FRD(i)
+#define UT_LOOP_RM UT_RM(i)
+
+#define VEC_LOAD(dst, func, inc) \
+  reg_t addr = RS1; \
+  UT_LOOP_START \
+    UT_LOOP_##dst = mmu.func(addr); \
+    addr += inc; \
+  UT_LOOP_END
+
+#define VEC_STORE(src, func, inc) \
+  reg_t addr = RS1; \
+  UT_LOOP_START \
+    mmu.func(addr, UT_LOOP_##src); \
+    addr += inc; \
+  UT_LOOP_END
+
+enum vt_command_t
+{
+  vt_command_stop,
+};
+
 #endif

diff --git a/riscv/insns/fld_v.h b/riscv/insns/fld_v.h
index e69de29bb2d1d6434b8b29ae775ad8c2e48c5391..c2d5072d1b98331f86b53fbfb8a82330786caaf7 100644 (file)
--- a/riscv/insns/fld_v.h
+++ b/riscv/insns/fld_v.h
@@ -0,0 +1,2 @@
+require_fp;
+VEC_LOAD(FRD, load_int64, 8);

diff --git a/riscv/insns/fldst_v.h b/riscv/insns/fldst_v.h
index e69de29bb2d1d6434b8b29ae775ad8c2e48c5391..60f99650ce97b04c1369badd9cb680931544e1fd 100644 (file)
--- a/riscv/insns/fldst_v.h
+++ b/riscv/insns/fldst_v.h
@@ -0,0 +1,2 @@
+require_fp;
+VEC_LOAD(FRD, load_int64, RS2);

diff --git a/riscv/insns/flw_v.h b/riscv/insns/flw_v.h
index e69de29bb2d1d6434b8b29ae775ad8c2e48c5391..1e54f7e8f059a1e10d736de7b1b01a80b1ff2f17 100644 (file)
--- a/riscv/insns/flw_v.h
+++ b/riscv/insns/flw_v.h
@@ -0,0 +1,2 @@
+require_fp;
+VEC_LOAD(FRD, load_int32, 4);

diff --git a/riscv/insns/flwst_v.h b/riscv/insns/flwst_v.h
index e69de29bb2d1d6434b8b29ae775ad8c2e48c5391..d11c6324dc19317e81aaa9ebca88252b74813528 100644 (file)
--- a/riscv/insns/flwst_v.h
+++ b/riscv/insns/flwst_v.h
@@ -0,0 +1,2 @@
+require_fp;
+VEC_LOAD(FRD, load_int32, RS2);

diff --git a/riscv/insns/fmov_su.h b/riscv/insns/fmov_su.h
index e69de29bb2d1d6434b8b29ae775ad8c2e48c5391..65d00baae7027031d59b033ab399a3805bd42901 100644 (file)
--- a/riscv/insns/fmov_su.h
+++ b/riscv/insns/fmov_su.h
@@ -0,0 +1,3 @@
+require_fp;
+demand(0 <= RS2 && RS2 < MAX_UTS, "ut not in range!");
+UT_FRD(RS2) = FRS1;

diff --git a/riscv/insns/fmov_sv.h b/riscv/insns/fmov_sv.h
index e69de29bb2d1d6434b8b29ae775ad8c2e48c5391..b689ed85aced2a0c71d693396799a3b38b2c1383 100644 (file)
--- a/riscv/insns/fmov_sv.h
+++ b/riscv/insns/fmov_sv.h
@@ -0,0 +1,4 @@
+require_fp;
+UT_LOOP_START
+  UT_LOOP_FRD = FRS1;
+UT_LOOP_END

diff --git a/riscv/insns/fmov_us.h b/riscv/insns/fmov_us.h
index e69de29bb2d1d6434b8b29ae775ad8c2e48c5391..4052739620f4fb9db361dbadebc832e2a53a2f89 100644 (file)
--- a/riscv/insns/fmov_us.h
+++ b/riscv/insns/fmov_us.h
@@ -0,0 +1,3 @@
+require_fp;
+demand(0 <= RS2 && RS2 < MAX_UTS, "ut not in range");
+FRD = UT_FRS1(RS2);

diff --git a/riscv/insns/fmov_vv.h b/riscv/insns/fmov_vv.h
index e69de29bb2d1d6434b8b29ae775ad8c2e48c5391..28269fd0388e68855a57e86fc96b926e57b911ae 100644 (file)
--- a/riscv/insns/fmov_vv.h
+++ b/riscv/insns/fmov_vv.h
@@ -0,0 +1,4 @@
+require_fp;
+UT_LOOP_START
+  UT_LOOP_FRD = UT_LOOP_FRS1;
+UT_LOOP_END

diff --git a/riscv/insns/fsd_v.h b/riscv/insns/fsd_v.h
index e69de29bb2d1d6434b8b29ae775ad8c2e48c5391..28871d54dfe3f46bc680be7347e04c75c58592bc 100644 (file)
--- a/riscv/insns/fsd_v.h
+++ b/riscv/insns/fsd_v.h
@@ -0,0 +1,2 @@
+require_fp;
+VEC_STORE(FRD, store_uint64, 8);

diff --git a/riscv/insns/fsdst_v.h b/riscv/insns/fsdst_v.h
index e69de29bb2d1d6434b8b29ae775ad8c2e48c5391..9a0b83d4b3bfcf861a7d90b9cfde7615b2f830a3 100644 (file)
--- a/riscv/insns/fsdst_v.h
+++ b/riscv/insns/fsdst_v.h
@@ -0,0 +1,2 @@
+require_fp;
+VEC_STORE(FRD, store_uint64, RS2);

diff --git a/riscv/insns/fsw_v.h b/riscv/insns/fsw_v.h
index e69de29bb2d1d6434b8b29ae775ad8c2e48c5391..6cb35805798ce6acb34a8e7df479baa7f0f09c27 100644 (file)
--- a/riscv/insns/fsw_v.h
+++ b/riscv/insns/fsw_v.h
@@ -0,0 +1,2 @@
+require_fp;
+VEC_STORE(FRD, store_uint32, 4);

diff --git a/riscv/insns/fswst_v.h b/riscv/insns/fswst_v.h
index e69de29bb2d1d6434b8b29ae775ad8c2e48c5391..9991e2c3d244dca5429576b13e12f9cafae73f33 100644 (file)
--- a/riscv/insns/fswst_v.h
+++ b/riscv/insns/fswst_v.h
@@ -0,0 +1,2 @@
+require_fp;
+VEC_STORE(FRD, store_uint32, RS2);

diff --git a/riscv/insns/lb_v.h b/riscv/insns/lb_v.h
index e69de29bb2d1d6434b8b29ae775ad8c2e48c5391..5246d9817391761071a06578db8e398a8dc9d531 100644 (file)
--- a/riscv/insns/lb_v.h
+++ b/riscv/insns/lb_v.h
@@ -0,0 +1 @@
+VEC_LOAD(RD, load_int8, 1);

diff --git a/riscv/insns/lbst_v.h b/riscv/insns/lbst_v.h
index e69de29bb2d1d6434b8b29ae775ad8c2e48c5391..91c8c3a472c6354972526507bf59ac7075f75ecb 100644 (file)
--- a/riscv/insns/lbst_v.h
+++ b/riscv/insns/lbst_v.h
@@ -0,0 +1 @@
+VEC_LOAD(RD, load_int8, RS2);

diff --git a/riscv/insns/lbu_v.h b/riscv/insns/lbu_v.h
index e69de29bb2d1d6434b8b29ae775ad8c2e48c5391..72d9af2d29972c04aceef125a3a8f2c2e8abc03d 100644 (file)
--- a/riscv/insns/lbu_v.h
+++ b/riscv/insns/lbu_v.h
@@ -0,0 +1 @@
+VEC_LOAD(RD, load_uint8, 1);

diff --git a/riscv/insns/lbust_v.h b/riscv/insns/lbust_v.h
index e69de29bb2d1d6434b8b29ae775ad8c2e48c5391..81ad75f4871521110069c2222a88c41afbea9415 100644 (file)
--- a/riscv/insns/lbust_v.h
+++ b/riscv/insns/lbust_v.h
@@ -0,0 +1 @@
+VEC_LOAD(RD, load_uint8, RS2);

diff --git a/riscv/insns/ld_v.h b/riscv/insns/ld_v.h
index e69de29bb2d1d6434b8b29ae775ad8c2e48c5391..124f9be154b3669b0baa91ae7d80f9ab6a8c6133 100644 (file)
--- a/riscv/insns/ld_v.h
+++ b/riscv/insns/ld_v.h
@@ -0,0 +1,2 @@
+require_xpr64;
+VEC_LOAD(RD, load_int64, 8);

diff --git a/riscv/insns/ldst_v.h b/riscv/insns/ldst_v.h
index e69de29bb2d1d6434b8b29ae775ad8c2e48c5391..84aa0fc5d58eee98886055d64638c689a2ff118a 100644 (file)
--- a/riscv/insns/ldst_v.h
+++ b/riscv/insns/ldst_v.h
@@ -0,0 +1,2 @@
+require_xpr64;
+VEC_LOAD(RD, load_int64, RS2);

diff --git a/riscv/insns/lh_v.h b/riscv/insns/lh_v.h
index e69de29bb2d1d6434b8b29ae775ad8c2e48c5391..29431105e886cb06acefc48eeea1d971abe32245 100644 (file)
--- a/riscv/insns/lh_v.h
+++ b/riscv/insns/lh_v.h
@@ -0,0 +1 @@
+VEC_LOAD(RD, load_int16, 2);

diff --git a/riscv/insns/lhst_v.h b/riscv/insns/lhst_v.h
index e69de29bb2d1d6434b8b29ae775ad8c2e48c5391..1bcd364a6a5acb350e3c071404f6f51f8d03937e 100644 (file)
--- a/riscv/insns/lhst_v.h
+++ b/riscv/insns/lhst_v.h
@@ -0,0 +1 @@
+VEC_LOAD(RD, load_int16, RS2);

diff --git a/riscv/insns/lhu_v.h b/riscv/insns/lhu_v.h
index e69de29bb2d1d6434b8b29ae775ad8c2e48c5391..b932aef9b520e65d16d20591da4c8d76543f75ee 100644 (file)
--- a/riscv/insns/lhu_v.h
+++ b/riscv/insns/lhu_v.h
@@ -0,0 +1 @@
+VEC_LOAD(RD, load_uint16, 2);

diff --git a/riscv/insns/lhust_v.h b/riscv/insns/lhust_v.h
index e69de29bb2d1d6434b8b29ae775ad8c2e48c5391..d1114286bca7a2aa17e7e6cf42632bda51dd0ec8 100644 (file)
--- a/riscv/insns/lhust_v.h
+++ b/riscv/insns/lhust_v.h
@@ -0,0 +1 @@
+VEC_LOAD(RD, load_uint16, RS2);

diff --git a/riscv/insns/lw_v.h b/riscv/insns/lw_v.h
index e69de29bb2d1d6434b8b29ae775ad8c2e48c5391..980a164e9c31a66ffb8c371f5262bc9ab005facf 100644 (file)
--- a/riscv/insns/lw_v.h
+++ b/riscv/insns/lw_v.h
@@ -0,0 +1 @@
+VEC_LOAD(RD, load_int32, 4);

diff --git a/riscv/insns/lwst_v.h b/riscv/insns/lwst_v.h
index e69de29bb2d1d6434b8b29ae775ad8c2e48c5391..735a6205697c672b5607158238bdf27c219f0001 100644 (file)
--- a/riscv/insns/lwst_v.h
+++ b/riscv/insns/lwst_v.h
@@ -0,0 +1 @@
+VEC_LOAD(RD, load_int32, RS2);

diff --git a/riscv/insns/lwu_v.h b/riscv/insns/lwu_v.h
index e69de29bb2d1d6434b8b29ae775ad8c2e48c5391..b1cdf3796675b20f8658845dc6ae548706dc7e1d 100644 (file)
--- a/riscv/insns/lwu_v.h
+++ b/riscv/insns/lwu_v.h
@@ -0,0 +1 @@
+VEC_LOAD(RD, load_uint32, 4);

diff --git a/riscv/insns/lwust_v.h b/riscv/insns/lwust_v.h
index e69de29bb2d1d6434b8b29ae775ad8c2e48c5391..7e0c006248ae39a136e78f4fe4184107f40e3c08 100644 (file)
--- a/riscv/insns/lwust_v.h
+++ b/riscv/insns/lwust_v.h
@@ -0,0 +1 @@
+VEC_LOAD(RD, load_uint32, RS2);

diff --git a/riscv/insns/mov_su.h b/riscv/insns/mov_su.h
index e69de29bb2d1d6434b8b29ae775ad8c2e48c5391..b55ab2f69f591a3e5499e0bc89e8967a200115cc 100644 (file)
--- a/riscv/insns/mov_su.h
+++ b/riscv/insns/mov_su.h
@@ -0,0 +1,2 @@
+demand(0 <= RS2 && RS2 < MAX_UTS, "ut not in range!");
+UT_RD(RS2) = RS1;

diff --git a/riscv/insns/mov_sv.h b/riscv/insns/mov_sv.h
index e69de29bb2d1d6434b8b29ae775ad8c2e48c5391..03bb29df3a1a436cbfa789c54d487ad41e5bf11f 100644 (file)
--- a/riscv/insns/mov_sv.h
+++ b/riscv/insns/mov_sv.h
@@ -0,0 +1,3 @@
+UT_LOOP_START
+  UT_LOOP_RD = RS1;
+UT_LOOP_END

diff --git a/riscv/insns/mov_us.h b/riscv/insns/mov_us.h
index e69de29bb2d1d6434b8b29ae775ad8c2e48c5391..05699a8d19698de0973876e6c29622489814bc95 100644 (file)
--- a/riscv/insns/mov_us.h
+++ b/riscv/insns/mov_us.h
@@ -0,0 +1,2 @@
+demand(0 <= RS2 && RS2 < MAX_UTS, "ut not in range");
+RD = UT_RS1(RS2);

diff --git a/riscv/insns/mov_vv.h b/riscv/insns/mov_vv.h
index e69de29bb2d1d6434b8b29ae775ad8c2e48c5391..2a1b0b6c32584eb266ef359beb9a82d092acad40 100644 (file)
--- a/riscv/insns/mov_vv.h
+++ b/riscv/insns/mov_vv.h
@@ -0,0 +1,3 @@
+UT_LOOP_START
+  UT_LOOP_RD = UT_LOOP_RS1;
+UT_LOOP_END

diff --git a/riscv/insns/sb_v.h b/riscv/insns/sb_v.h
index e69de29bb2d1d6434b8b29ae775ad8c2e48c5391..81e35130693000bf0ed4cb7a923d187d7c549dfd 100644 (file)
--- a/riscv/insns/sb_v.h
+++ b/riscv/insns/sb_v.h
@@ -0,0 +1 @@
+VEC_STORE(RD, store_uint8, 1);

diff --git a/riscv/insns/sbst_v.h b/riscv/insns/sbst_v.h
index e69de29bb2d1d6434b8b29ae775ad8c2e48c5391..2d7c59bca1c77f936c3e33e7309d574cb9f3794e 100644 (file)
--- a/riscv/insns/sbst_v.h
+++ b/riscv/insns/sbst_v.h
@@ -0,0 +1 @@
+VEC_STORE(RD, store_uint8, RS2);

diff --git a/riscv/insns/sd_v.h b/riscv/insns/sd_v.h
index e69de29bb2d1d6434b8b29ae775ad8c2e48c5391..330e1b0017f13945024903017f3815c47baf3ae4 100644 (file)
--- a/riscv/insns/sd_v.h
+++ b/riscv/insns/sd_v.h
@@ -0,0 +1,2 @@
+require_xpr64;
+VEC_STORE(RD, store_uint64, 8);

diff --git a/riscv/insns/sdst_v.h b/riscv/insns/sdst_v.h
index e69de29bb2d1d6434b8b29ae775ad8c2e48c5391..d3e74d32b96df8bbd400dc2524f77b25bfaa9f68 100644 (file)
--- a/riscv/insns/sdst_v.h
+++ b/riscv/insns/sdst_v.h
@@ -0,0 +1,2 @@
+require_xpr64;
+VEC_STORE(RD, store_uint64, RS2);

diff --git a/riscv/insns/setvl.h b/riscv/insns/setvl.h
index e69de29bb2d1d6434b8b29ae775ad8c2e48c5391..5b611db0633324129645aa9971c1811a8316b18d 100644 (file)
--- a/riscv/insns/setvl.h
+++ b/riscv/insns/setvl.h
@@ -0,0 +1,2 @@
+setvl(RS1);
+RD = VL;

diff --git a/riscv/insns/sh_v.h b/riscv/insns/sh_v.h
index e69de29bb2d1d6434b8b29ae775ad8c2e48c5391..fdfe6fe3d82ea957a275e790da472dc0fa608f83 100644 (file)
--- a/riscv/insns/sh_v.h
+++ b/riscv/insns/sh_v.h
@@ -0,0 +1 @@
+VEC_STORE(RD, store_uint16, 2);

diff --git a/riscv/insns/shst_v.h b/riscv/insns/shst_v.h
index e69de29bb2d1d6434b8b29ae775ad8c2e48c5391..4f4044ce073f7107389aa787fb777591d232ed98 100644 (file)
--- a/riscv/insns/shst_v.h
+++ b/riscv/insns/shst_v.h
@@ -0,0 +1 @@
+VEC_STORE(RD, store_uint16, RS2);

diff --git a/riscv/insns/stop.h b/riscv/insns/stop.h
index e69de29bb2d1d6434b8b29ae775ad8c2e48c5391..cbf69dc2bae97aebcb15ea6073cb4206e3bc1c51 100644 (file)
--- a/riscv/insns/stop.h
+++ b/riscv/insns/stop.h
@@ -0,0 +1,2 @@
+utmode = false;
+throw vt_command_stop;

diff --git a/riscv/insns/sw_v.h b/riscv/insns/sw_v.h
index e69de29bb2d1d6434b8b29ae775ad8c2e48c5391..276da954f7a8f2258e33857c1cf1f8530bd2c7f2 100644 (file)
--- a/riscv/insns/sw_v.h
+++ b/riscv/insns/sw_v.h
@@ -0,0 +1 @@
+VEC_STORE(RD, store_uint32, 4);

diff --git a/riscv/insns/swst_v.h b/riscv/insns/swst_v.h
index e69de29bb2d1d6434b8b29ae775ad8c2e48c5391..08b198cef73bdda0bf48a061c7fbc91351894406 100644 (file)
--- a/riscv/insns/swst_v.h
+++ b/riscv/insns/swst_v.h
@@ -0,0 +1 @@
+VEC_STORE(RD, store_uint32, RS2);

diff --git a/riscv/insns/utidx.h b/riscv/insns/utidx.h
index e69de29bb2d1d6434b8b29ae775ad8c2e48c5391..70336acd0f04c7bcd7e3ae5d2036093222534d00 100644 (file)
--- a/riscv/insns/utidx.h
+++ b/riscv/insns/utidx.h
@@ -0,0 +1 @@
+RD = utidx;

diff --git a/riscv/insns/vcfgivl.h b/riscv/insns/vcfgivl.h
index e69de29bb2d1d6434b8b29ae775ad8c2e48c5391..c870f673121da78ac9f1986ee8ba387a29c2ed9c 100644 (file)
--- a/riscv/insns/vcfgivl.h
+++ b/riscv/insns/vcfgivl.h
@@ -0,0 +1,5 @@
+nxpr_use = SIMM & 0x3f;
+nfpr_use = (SIMM >> 6) & 0x3f;
+vcfg();
+setvl(RS1);
+RD = VL;

diff --git a/riscv/insns/vf.h b/riscv/insns/vf.h
index e69de29bb2d1d6434b8b29ae775ad8c2e48c5391..eff542cf0f14d0a17fffc09ce0faa993a033a607 100644 (file)
--- a/riscv/insns/vf.h
+++ b/riscv/insns/vf.h
@@ -0,0 +1,7 @@
+for (int i=0; i<VL; i++)
+{
+  uts[i]->pc = RS1+SIMM;
+  uts[i]->utmode = true;
+  while (uts[i]->utmode)
+    uts[i]->step(n, noisy);
+}

diff --git a/riscv/processor.cc b/riscv/processor.cc
index 8aa29661f3fc339f466f6f0d3b4914ddc2f723ae..99da902738c90fad01d205257efb84ee0c1972f5 100644 (file)
--- a/riscv/processor.cc
+++ b/riscv/processor.cc
@@ -32,6 +32,17 @@ processor_t::processor_t(sim_t* _sim, char* _mem, size_t _memsz)
 
   memset(counters,0,sizeof(counters));
 
+  // vector stuff
+  utidx = -1;
+  vlmax = 8;
+  vl = 0;
+  nxpr_all = 256;
+  nfpr_all = 256;
+  nxpr_use = 0;
+  nfpr_use = 0;
+  for (int i=0; i<MAX_UTS; i++)
+    uts[i] = NULL;
+
   // a few assumptions about endianness, including freg_t union
   static_assert(BYTE_ORDER == LITTLE_ENDIAN);
   static_assert(sizeof(freg_t) == 8);
@@ -41,9 +52,16 @@ processor_t::processor_t(sim_t* _sim, char* _mem, size_t _memsz)
   static_assert(sizeof(uint128_t) == 16 && sizeof(int128_t) == 16);
 }
 
-void processor_t::init(uint32_t _id)
+void processor_t::init(uint32_t _id, char* _mem, size_t _memsz)
 {
   id = _id;
+
+  for (int i=0; i<MAX_UTS; i++)
+  {
+    uts[i] = new processor_t(sim, _mem, _memsz);
+    uts[i]->set_sr(uts[i]->sr | SR_EF);
+    uts[i]->utidx = i;
+  }
 }
 
 void processor_t::set_sr(uint32_t val)
@@ -67,6 +85,25 @@ void processor_t::set_fsr(uint32_t val)
   fsr = val & ~FSR_ZERO;
 }
 
+void processor_t::vcfg()
+{
+  if (nxpr_use == 0 && nfpr_use == 0)
+    vlmax = 8;
+  else if (nfpr_use == 0)
+    vlmax = (nxpr_all-1) / (nxpr_use-1);
+  else if (nxpr_use == 0)
+    vlmax = (nfpr_all-1) / (nfpr_use-1);
+  else
+    vlmax = std::min((nxpr_all-1) / (nxpr_use-1), (nfpr_all-1) / (nfpr_use-1));
+
+  vlmax = std::min(vlmax, MAX_UTS);
+}
+
+void processor_t::setvl(int vlapp)
+{
+  vl = std::min(vlmax, vlapp);
+}
+
 void processor_t::step(size_t n, bool noisy)
 {
   size_t i = 0;
@@ -101,6 +138,11 @@ void processor_t::step(size_t n, bool noisy)
     i++;
     take_trap(t,noisy);
   }
+  catch(vt_command_t cmd)
+  {
+    if (cmd == vt_command_stop)
+      return;
+  }
 }
 
 void processor_t::take_trap(trap_t t, bool noisy)

diff --git a/riscv/processor.h b/riscv/processor.h
index c1c65ce2f1338d076abb0aa1fa6e85c42c63cc03..34c31ac396725f13b35f4895abc04272e9800594 100644 (file)
--- a/riscv/processor.h
+++ b/riscv/processor.h
@@ -6,13 +6,15 @@
 #include "trap.h"
 #include "mmu.h"
 
+#define MAX_UTS 32
+
 class sim_t;
 
 class processor_t
 {
 public:
   processor_t(sim_t* _sim, char* _mem, size_t _memsz);
-  void init(uint32_t _id);
+  void init(uint32_t _id, char* _mem, size_t _memsz);
   void step(size_t n, bool noisy);
 
 private:
@@ -55,6 +57,20 @@ private:
   void take_trap(trap_t t, bool noisy);
   void disasm(insn_t insn, reg_t pc);
 
+  // vector stuff
+  void vcfg();
+  void setvl(int vlapp);
+
+  bool utmode;
+  int utidx;
+  int vlmax;
+  int vl;
+  int nxpr_all;
+  int nfpr_all;
+  int nxpr_use;
+  int nfpr_use;
+  processor_t* uts[MAX_UTS];
+
   friend class sim_t;
 };
 

diff --git a/riscv/sim.cc b/riscv/sim.cc
index 56326b5d373d19df4424238a5b2c6db51dfaff73..fbea37444f4f7f30b8698f0c4ded13911d43ef4e 100644 (file)
--- a/riscv/sim.cc
+++ b/riscv/sim.cc
@@ -15,7 +15,7 @@ sim_t::sim_t(int _nprocs, size_t _memsz, appserver_link_t* _applink)
   demand(mem != MAP_FAILED, "couldn't allocate target machine's memory");
 
   for(int i = 0; i < (int)procs.size(); i++)
-    procs[i].init(i);
+    procs[i].init(i, mem, memsz);
 
   applink->init(this);
 }