[sim] add vt stuff

[riscv-isa-sim.git] / riscv / insns / lwst_v.h

diff --git a/riscv/insns/lwst_v.h b/riscv/insns/lwst_v.h
index e69de29bb2d1d6434b8b29ae775ad8c2e48c5391..735a6205697c672b5607158238bdf27c219f0001 100644 (file)
--- a/riscv/insns/lwst_v.h
+++ b/riscv/insns/lwst_v.h
@@ -0,0 +1 @@
+VEC_LOAD(RD, load_int32, RS2);