[sim] add vt stuff

[riscv-isa-sim.git] / riscv / insns / setvl.h

diff --git a/riscv/insns/setvl.h b/riscv/insns/setvl.h
index e69de29bb2d1d6434b8b29ae775ad8c2e48c5391..5b611db0633324129645aa9971c1811a8316b18d 100644 (file)
--- a/riscv/insns/setvl.h
+++ b/riscv/insns/setvl.h
@@ -0,0 +1,2 @@
+setvl(RS1);
+RD = VL;