dbus -> dmi

[riscv-isa-sim.git] / riscv / jtag_dtm.cc

diff --git a/riscv/jtag_dtm.cc b/riscv/jtag_dtm.cc
index 5fcc30305dd3082e6a6b899e6ea2f0bf183b876d..84f13f8d7bd9de96fa8dc5fa6d2dd8e4fd7f958f 100644 (file)
--- a/riscv/jtag_dtm.cc
+++ b/riscv/jtag_dtm.cc
@@ -3,8 +3,9 @@
 #include "decode.h"
 #include "jtag_dtm.h"
 #include "debug_module.h"
+#include "debug_defines.h"
 
-#if 1
+#if 0
 #  define D(x) x
 #else
 #  define D(x)
@@ -22,24 +23,25 @@ enum {
 #define DTMCONTROL_IDLE         (7<<12)
 #define DTMCONTROL_DBUSRESET    (1<<16)
 
-#define DBUS_OP                 3
-#define DBUS_DATA               (0xffffffffL<<2)
-#define DBUS_ADDRESS            ((1L<<(abits+34)) - (1L<<34))
+#define DMI_OP                 3
+#define DMI_DATA               (0xffffffffL<<2)
+#define DMI_ADDRESS            ((1L<<(abits+34)) - (1L<<34))
 
-#define DBUS_OP_STATUS_SUCCESS 0
-#define DBUS_OP_STATUS_RESERVED        1
-#define DBUS_OP_STATUS_FAILED  2
-#define DBUS_OP_STATUS_BUSY    3
+#define DMI_OP_STATUS_SUCCESS  0
+#define DMI_OP_STATUS_RESERVED 1
+#define DMI_OP_STATUS_FAILED   2
+#define DMI_OP_STATUS_BUSY     3
 
-#define DBUS_OP_NOP            0
-#define DBUS_OP_READ           1
-#define DBUS_OP_READ_WRITE     2
-#define DBUS_OP_RESERVED       3
+#define DMI_OP_NOP             0
+#define DMI_OP_READ            1
+#define DMI_OP_READ_WRITE      2
+#define DMI_OP_RESERVED        3
 
 jtag_dtm_t::jtag_dtm_t(debug_module_t *dm) :
   dm(dm),
-  dtmcontrol((abits << 4) | 1),
-  dbus(0),
+  _tck(false), _tms(false), _tdi(false), _tdo(false),
+  dtmcontrol((abits << DTM_DTMCONTROL_ABITS_OFFSET) | 1),
+  dmi(DMI_OP_STATUS_FAILED << DTM_DMI_OP_OFFSET),
   state(TEST_LOGIC_RESET)
 {
 }
@@ -109,8 +111,11 @@ void jtag_dtm_t::set_pins(bool tck, bool tms, bool tdi) {
     }
   }
 
-  D(fprintf(stderr, "state=%2d, tdi=%d, tdo=%d, tms=%d, tck=%d, ir=0x%02x, dr=0x%lx\n",
+  /*
+  D(fprintf(stderr, "state=%2d, tdi=%d, tdo=%d, tms=%d, tck=%d, ir=0x%02x, "
+        "dr=0x%lx\n",
         state, _tdi, _tdo, _tms, _tck, ir, dr));
+        */
 
   _tck = tck;
   _tms = tms;
@@ -129,7 +134,7 @@ void jtag_dtm_t::capture_dr()
       dr_length = 32;
       break;
     case IR_DBUS:
-      dr = dbus;
+      dr = dmi;
       dr_length = abits + 34;
       break;
     default:
@@ -147,20 +152,31 @@ void jtag_dtm_t::update_dr()
   switch (ir) {
     case IR_DBUS:
       {
-        unsigned op = get_field(dr, DBUS_OP);
-        uint32_t data = get_field(dr, DBUS_DATA);
-        unsigned address = get_field(dr, DBUS_ADDRESS);
-
-        dbus = dr;
-
-        if (op == DBUS_OP_READ || op == DBUS_OP_READ_WRITE) {
-          dbus = set_field(dbus, DBUS_DATA, dm->dmi_read(address));
+        unsigned op = get_field(dr, DMI_OP);
+        uint32_t data = get_field(dr, DMI_DATA);
+        unsigned address = get_field(dr, DMI_ADDRESS);
+
+        dmi = dr;
+
+        bool success = true;
+        if (op == DMI_OP_READ || op == DMI_OP_READ_WRITE) {
+          uint32_t value;
+          if (dm->dmi_read(address, &value)) {
+            dmi = set_field(dmi, DMI_DATA, value);
+          } else {
+            success = false;
+          }
         }
-        if (op == DBUS_OP_READ_WRITE) {
-          dm->dmi_write(address, data);
+        if (success && op == DMI_OP_READ_WRITE) {
+          success = dm->dmi_write(address, data);
         }
 
-        dbus = set_field(dbus, DBUS_OP, DBUS_OP_STATUS_SUCCESS);
+        if (success) {
+          dmi = set_field(dmi, DMI_OP, DMI_OP_STATUS_SUCCESS);
+        } else {
+          dmi = set_field(dmi, DMI_OP, DMI_OP_STATUS_FAILED);
+        }
+        D(fprintf(stderr, "dmi=0x%lx\n", dmi));
       }
       break;
   }