[xcc,sim] eliminated vectored traps

[riscv-isa-sim.git] / riscv / mmu.h

diff --git a/riscv/mmu.h b/riscv/mmu.h
index 9bfbeac31757ddeecb9591712deec7c50b11f7e5..1b8a422e20a45e5f787839b517062e99c0bb843c 100644 (file)
--- a/riscv/mmu.h
+++ b/riscv/mmu.h
@@ -50,9 +50,9 @@ private:
   {
     if(addr & (size-1))
     {
+      badvaddr = addr;
       if(fetch)
         throw trap_instruction_address_misaligned;
-      badvaddr = addr;
       throw trap_data_address_misaligned;
     }
   }
@@ -61,9 +61,9 @@ private:
   {
     if(addr >= memsz || addr + size > memsz)
     {
+      badvaddr = addr;
       if(fetch)
         throw trap_instruction_access_fault;
-      badvaddr = addr;
       throw store ? trap_store_access_fault : trap_load_access_fault;
     }
   }