[xcc,sim,opcodes] more rvc instructions and bug fixes

[riscv-isa-sim.git] / riscv / mmu.h

diff --git a/riscv/mmu.h b/riscv/mmu.h
index efaea3e3da839ab8ffe31de3299215a3c697483e..c61eb80af2fc94118f6e1a73f216eaf4f7a173c4 100644 (file)
--- a/riscv/mmu.h
+++ b/riscv/mmu.h
@@ -25,9 +25,7 @@ public:
     uint16_t hi = *(uint16_t*)(mem+addr+2);
 
     insn_t insn; 
-    insn.bits = lo;
-    if((lo & 0x3) == 0x3)
-      insn.bits |= (uint32_t)hi << 16;
+    insn.bits = lo | ((uint32_t)hi << 16);
 
     return insn;
   }