#include "sim.h"
#include "mmu.h"
#include "disasm.h"
-#include "gdbserver.h"
#include <cinttypes>
#include <cmath>
#include <cstdlib>
processor_t::processor_t(const char* isa, sim_t* sim, uint32_t id,
bool halt_on_reset)
- : debug(false), sim(sim), ext(NULL), id(id), halt_on_reset(halt_on_reset)
+ : debug(false), halt_request(false), sim(sim), ext(NULL), id(id),
+ halt_on_reset(halt_on_reset)
{
parse_isa_string(isa);
register_base_instructions();
// advertise support for supervisor and user modes
isa |= 1L << ('s' - 'a');
isa |= 1L << ('u' - 'a');
+
+ max_isa = isa;
}
void state_t::reset()
pc = DEFAULT_RSTVEC;
mtvec = DEFAULT_MTVEC;
load_reservation = -1;
+ tselect = 0;
+ for (unsigned int i = 0; i < num_triggers; i++)
+ mcontrol[i].type = 2;
}
void processor_t::set_debug(bool value)
throw trap_t(((reg_t)1 << (max_xlen-1)) | which);
}
+// Count number of contiguous 0 bits starting from the LSB.
static int ctz(reg_t val)
{
int res = 0;
state.dcsr.prv = state.prv;
set_privilege(PRV_M);
state.dpc = state.pc;
- state.pc = DEBUG_ROM_START;
- //debug = true; // TODO
+ state.pc = debug_rom_entry();
}
void processor_t::take_trap(trap_t& t, reg_t epc)
t.get_badaddr());
}
+ if (state.dcsr.cause) {
+ if (t.cause() == CAUSE_BREAKPOINT) {
+ state.pc = debug_rom_entry();
+ } else {
+ state.pc = DEBUG_ROM_EXCEPTION;
+ }
+ return;
+ }
+
if (t.cause() == CAUSE_BREAKPOINT && (
(state.prv == PRV_M && state.dcsr.ebreakm) ||
(state.prv == PRV_H && state.dcsr.ebreakh) ||
return;
}
- if (state.dcsr.cause) {
- state.pc = DEBUG_ROM_EXCEPTION;
- return;
- }
-
// by default, trap to M-mode, unless delegated to S-mode
reg_t bit = t.cause();
reg_t deleg = state.medeleg;
| SSTATUS_XS | SSTATUS_PUM;
return set_csr(CSR_MSTATUS, (state.mstatus & ~mask) | (val & mask));
}
- case CSR_SIP:
- return set_csr(CSR_MIP,
- (state.mip & ~state.mideleg) | (val & state.mideleg));
+ case CSR_SIP: {
+ reg_t mask = MIP_SSIP & state.mideleg;
+ return set_csr(CSR_MIP, (state.mip & ~mask) | (val & mask));
+ }
case CSR_SIE:
return set_csr(CSR_MIE,
(state.mie & ~state.mideleg) | (val & state.mideleg));
case CSR_MSCRATCH: state.mscratch = val; break;
case CSR_MCAUSE: state.mcause = val; break;
case CSR_MBADADDR: state.mbadaddr = val; break;
+ case CSR_MISA: {
+ if (!(val & (1L << ('F' - 'A'))))
+ val &= ~(1L << ('D' - 'A'));
+
+ // allow MAFDC bits in MISA to be modified
+ reg_t mask = 0;
+ mask |= 1L << ('M' - 'A');
+ mask |= 1L << ('A' - 'A');
+ mask |= 1L << ('F' - 'A');
+ mask |= 1L << ('D' - 'A');
+ mask |= 1L << ('C' - 'A');
+ mask &= max_isa;
+
+ isa = (val & mask) | (isa & ~mask);
+ break;
+ }
+ case CSR_TSELECT:
+ if (val < state.num_triggers) {
+ state.tselect = val;
+ }
+ break;
+ case CSR_TDATA1:
+ {
+ mcontrol_t *mc = &state.mcontrol[state.tselect];
+ if (mc->dmode && !state.dcsr.cause) {
+ break;
+ }
+ mc->dmode = get_field(val, MCONTROL_DMODE(xlen));
+ mc->select = get_field(val, MCONTROL_SELECT);
+ mc->timing = get_field(val, MCONTROL_TIMING);
+ mc->action = (mcontrol_action_t) get_field(val, MCONTROL_ACTION);
+ mc->chain = get_field(val, MCONTROL_CHAIN);
+ mc->match = (mcontrol_match_t) get_field(val, MCONTROL_MATCH);
+ mc->m = get_field(val, MCONTROL_M);
+ mc->h = get_field(val, MCONTROL_H);
+ mc->s = get_field(val, MCONTROL_S);
+ mc->u = get_field(val, MCONTROL_U);
+ mc->execute = get_field(val, MCONTROL_EXECUTE);
+ mc->store = get_field(val, MCONTROL_STORE);
+ mc->load = get_field(val, MCONTROL_LOAD);
+ // Assume we're here because of csrw.
+ if (mc->execute)
+ mc->timing = 0;
+ trigger_updated();
+ }
+ break;
+ case CSR_TDATA2:
+ if (state.mcontrol[state.tselect].dmode && !state.dcsr.cause) {
+ break;
+ }
+ if (state.tselect < state.num_triggers) {
+ state.tdata2[state.tselect] = val;
+ }
+ break;
case CSR_DCSR:
state.dcsr.prv = get_field(val, DCSR_PRV);
state.dcsr.step = get_field(val, DCSR_STEP);
case CSR_MTVEC: return state.mtvec;
case CSR_MEDELEG: return state.medeleg;
case CSR_MIDELEG: return state.mideleg;
- case CSR_TSELECT: return 0;
- case CSR_TDATA1: return 0;
- case CSR_TDATA2: return 0;
+ case CSR_TSELECT: return state.tselect;
+ case CSR_TDATA1:
+ if (state.tselect < state.num_triggers) {
+ reg_t v = 0;
+ mcontrol_t *mc = &state.mcontrol[state.tselect];
+ v = set_field(v, MCONTROL_TYPE(xlen), mc->type);
+ v = set_field(v, MCONTROL_DMODE(xlen), mc->dmode);
+ v = set_field(v, MCONTROL_MASKMAX(xlen), mc->maskmax);
+ v = set_field(v, MCONTROL_SELECT, mc->select);
+ v = set_field(v, MCONTROL_TIMING, mc->timing);
+ v = set_field(v, MCONTROL_ACTION, mc->action);
+ v = set_field(v, MCONTROL_CHAIN, mc->chain);
+ v = set_field(v, MCONTROL_MATCH, mc->match);
+ v = set_field(v, MCONTROL_M, mc->m);
+ v = set_field(v, MCONTROL_H, mc->h);
+ v = set_field(v, MCONTROL_S, mc->s);
+ v = set_field(v, MCONTROL_U, mc->u);
+ v = set_field(v, MCONTROL_EXECUTE, mc->execute);
+ v = set_field(v, MCONTROL_STORE, mc->store);
+ v = set_field(v, MCONTROL_LOAD, mc->load);
+ return v;
+ } else {
+ return 0;
+ }
+ break;
+ case CSR_TDATA2:
+ if (state.tselect < state.num_triggers) {
+ return state.tdata2[state.tselect];
+ } else {
+ return 0;
+ }
+ break;
case CSR_TDATA3: return 0;
case CSR_DCSR:
{
return false;
}
}
+
+void processor_t::trigger_updated()
+{
+ mmu->flush_tlb();
+ mmu->check_triggers_fetch = false;
+ mmu->check_triggers_load = false;
+ mmu->check_triggers_store = false;
+
+ for (unsigned i = 0; i < state.num_triggers; i++) {
+ if (state.mcontrol[i].execute) {
+ mmu->check_triggers_fetch = true;
+ }
+ if (state.mcontrol[i].load) {
+ mmu->check_triggers_load = true;
+ }
+ if (state.mcontrol[i].store) {
+ mmu->check_triggers_store = true;
+ }
+ }
+}
projects / riscv-isa-sim.git / blobdiff