gdb can now read spike memory.

[riscv-isa-sim.git] / riscv / processor.h

diff --git a/riscv/processor.h b/riscv/processor.h
index e342ab07170d4c09398180c9af174ba9b8e67104..3adf9903471f24846420d92aa5da9f9b56f83cf0 100644 (file)
--- a/riscv/processor.h
+++ b/riscv/processor.h
@@ -45,8 +45,8 @@ struct state_t
   reg_t mstatus;
   reg_t mepc;
   reg_t mbadaddr;
-  reg_t mtimecmp;
   reg_t mscratch;
+  reg_t mtvec;
   reg_t mcause;
   reg_t minstret;
   reg_t mie;
@@ -61,8 +61,6 @@ struct state_t
   reg_t stvec;
   reg_t sptbr;
   reg_t scause;
-  reg_t tohost;
-  reg_t fromhost;
   uint32_t fflags;
   uint32_t frm;
   bool serialized; // whether timer CSRs are in a well-defined state
@@ -136,7 +134,9 @@ private:
 
   friend class sim_t;
   friend class mmu_t;
+  friend class rtc_t;
   friend class extension_t;
+  friend class gdbserver_t;
 
   void parse_isa_string(const char* isa);
   void build_opcode_map();