Added PC histogram option.

[riscv-isa-sim.git] / riscv / processor.h

diff --git a/riscv/processor.h b/riscv/processor.h
index e27aa823eeaad33022fa26edf9b49a41b6e85fcf..58c31cb3eb4c9309fc0adad599cc88f500b5c6c9 100644 (file)
--- a/riscv/processor.h
+++ b/riscv/processor.h
@@ -5,8 +5,8 @@
 #include "decode.h"
 #include "config.h"
 #include <cstring>
-#include <memory>
 #include <vector>
+#include <map>
 
 class processor_t;
 class mmu_t;
@@ -24,6 +24,12 @@ struct insn_desc_t
   insn_func_t rv64;
 };
 
+struct commit_log_reg_t
+{
+  uint32_t addr;
+  reg_t data;
+};
+
 // architectural state of a RISC-V hart
 struct state_t
 {
@@ -50,6 +56,10 @@ struct state_t
   uint32_t frm;
 
   reg_t load_reservation;
+
+#ifdef RISCV_ENABLE_COMMITLOG
+  commit_log_reg_t log_reg_write;
+#endif
 };
 
 // this class represents one processor in a RISC-V machine.
@@ -60,17 +70,20 @@ public:
   ~processor_t();
 
   void set_debug(bool value);
+  void set_histogram(bool value);
   void reset(bool value);
   void step(size_t n); // run for n cycles
   void deliver_ipi(); // register an interprocessor interrupt
   bool running() { return run; }
   reg_t set_pcr(int which, reg_t val);
+  void set_fromhost(reg_t val);
   void set_interrupt(int which, bool on);
   reg_t get_pcr(int which);
   mmu_t* get_mmu() { return mmu; }
   state_t* get_state() { return &state; }
   extension_t* get_extension() { return ext; }
   void yield_load_reservation() { state.load_reservation = (reg_t)-1; }
+  void update_histogram(size_t pc);
 
   void register_insn(insn_desc_t);
   void register_extension(extension_t*);
@@ -79,25 +92,26 @@ private:
   sim_t* sim;
   mmu_t* mmu; // main memory is always accessed via the mmu
   extension_t* ext;
-  std::unique_ptr<disassembler_t> disassembler;
+  disassembler_t* disassembler;
   state_t state;
   uint32_t id;
   bool run; // !reset
   bool debug;
+  bool histogram_enabled;
   bool rv64;
 
   std::vector<insn_desc_t> instructions;
   std::vector<insn_desc_t*> opcode_map;
   std::vector<insn_desc_t> opcode_store;
+  std::map<size_t,size_t> pc_histogram;
 
   void take_interrupt(); // take a trap if any interrupts are pending
-  void take_trap(reg_t pc, trap_t& t); // take an exception
+  void take_trap(trap_t& t); // take an exception
   void disasm(insn_t insn); // disassemble and print an instruction
 
   friend class sim_t;
   friend class mmu_t;
   friend class extension_t;
-  friend class htif_isasim_t;
 
   void build_opcode_map();
   insn_func_t decode_insn(insn_t insn);