debug: Compiles again with new debug_defines.h file, but not tested.

[riscv-isa-sim.git] / riscv / riscv.mk.in

diff --git a/riscv/riscv.mk.in b/riscv/riscv.mk.in
index 279fbde8130e17656bf7a29a18e5ba2a23a17831..40054cfbaa289793f4ca8051dc1edf0157be20e4 100644 (file)
--- a/riscv/riscv.mk.in
+++ b/riscv/riscv.mk.in
@@ -7,7 +7,6 @@ riscv_subproject_deps = \
 riscv_install_prog_srcs = \
 
 riscv_hdrs = \
-       htif.h \
        common.h \
        decode.h \
        devices.h \
@@ -24,14 +23,14 @@ riscv_hdrs = \
        rocc.h \
        insn_template.h \
        mulhi.h \
-       gdbserver.h \
        debug_module.h \
+       remote_bitbang.h \
+       jtag_dtm.h \
 
 riscv_precompiled_hdrs = \
        insn_template.h \
 
 riscv_srcs = \
-       htif.cc \
        processor.cc \
        execute.cc \
        sim.cc \
@@ -46,9 +45,10 @@ riscv_srcs = \
        regnames.cc \
        devices.cc \
        rom.cc \
-       rtc.cc \
-       gdbserver.cc \
+       clint.cc \
        debug_module.cc \
+       remote_bitbang.cc \
+       jtag_dtm.cc \
        $(riscv_gen_srcs) \
 
 riscv_test_srcs =
@@ -134,6 +134,7 @@ riscv_insn_list = \
        divu \
        divuw \
        divw \
+       dret \
        ebreak \
        ecall \
        fadd_d \
@@ -228,7 +229,7 @@ riscv_insn_list = \
        sc_d \
        sc_w \
        sd \
-       sfence_vm \
+       sfence_vma \
        sh \
        sll \
        slli \