debug: Compiles again with new debug_defines.h file, but not tested.

diff --git a/riscv/debug_module.cc b/riscv/debug_module.cc
index 43dc7372bcd896bb4a11cb7ce3e38f5003c95ef5..7b113abc0fe570e20d8fc1d483f4e53aeb6d9854 100644 (file)
--- a/riscv/debug_module.cc
+++ b/riscv/debug_module.cc
@@ -369,16 +369,10 @@ bool debug_module_t::perform_abstract_command()
       write32(debug_rom_code, 1, ebreak());
     }
 
-    if (get_field(command, AC_ACCESS_REGISTER_PREEXEC)) {
-      write32(debug_rom_entry, dmcontrol.hartsel,
-          jal(ZERO, DEBUG_RAM_START - (DEBUG_ROM_ENTRY + 4 * dmcontrol.hartsel)));
-      next_action =
-        jal(ZERO, DEBUG_ROM_CODE - (DEBUG_ROM_ENTRY + 4 * dmcontrol.hartsel));
-    } else {
-      write32(debug_rom_entry, dmcontrol.hartsel,
-          jal(ZERO, DEBUG_ROM_CODE - (DEBUG_ROM_ENTRY + 4 * dmcontrol.hartsel)));
-    }
-
+    //TODO: Consider 'transfer' bit.
+    write32(debug_rom_entry, dmcontrol.hartsel,
+            jal(ZERO, DEBUG_ROM_CODE - (DEBUG_ROM_ENTRY + 4 * dmcontrol.hartsel)));
+    
     write32(debug_rom_exception, dmcontrol.hartsel,
         jal(ZERO, (DEBUG_ROM_ENTRY + 4 * dmcontrol.hartsel) - DEBUG_ROM_EXCEPTION));
     abstractcs.busy = true;

diff --git a/riscv/riscv.mk.in b/riscv/riscv.mk.in
index 9cd8f4dbef2c08599371c3880e0498d260e19eaf..40054cfbaa289793f4ca8051dc1edf0157be20e4 100644 (file)
--- a/riscv/riscv.mk.in
+++ b/riscv/riscv.mk.in
@@ -45,9 +45,7 @@ riscv_srcs = \
        regnames.cc \
        devices.cc \
        rom.cc \
-       rtc.cc \
        clint.cc \
-       gdbserver.cc \
        debug_module.cc \
        remote_bitbang.cc \
        jtag_dtm.cc \