debug: Compiles again with new debug_defines.h file, but not tested.

[riscv-isa-sim.git] / riscv / riscv.mk.in

diff --git a/riscv/riscv.mk.in b/riscv/riscv.mk.in
index 7d71fb51f3faf0fd81ae70ce3e70d981128fadf4..40054cfbaa289793f4ca8051dc1edf0157be20e4 100644 (file)
--- a/riscv/riscv.mk.in
+++ b/riscv/riscv.mk.in
@@ -7,9 +7,9 @@ riscv_subproject_deps = \
 riscv_install_prog_srcs = \
 
 riscv_hdrs = \
-       htif.h \
        common.h \
        decode.h \
+       devices.h \
        disasm.h \
        mmu.h \
        processor.h \
@@ -18,16 +18,19 @@ riscv_hdrs = \
        encoding.h \
        cachesim.h \
        memtracer.h \
+       tracer.h \
        extension.h \
        rocc.h \
        insn_template.h \
        mulhi.h \
+       debug_module.h \
+       remote_bitbang.h \
+       jtag_dtm.h \
 
 riscv_precompiled_hdrs = \
        insn_template.h \
 
 riscv_srcs = \
-       htif.cc \
        processor.cc \
        execute.cc \
        sim.cc \
@@ -41,6 +44,11 @@ riscv_srcs = \
        rocc.cc \
        regnames.cc \
        devices.cc \
+       rom.cc \
+       clint.cc \
+       debug_module.cc \
+       remote_bitbang.cc \
+       jtag_dtm.cc \
        $(riscv_gen_srcs) \
 
 riscv_test_srcs =
@@ -126,6 +134,9 @@ riscv_insn_list = \
        divu \
        divuw \
        divw \
+       dret \
+       ebreak \
+       ecall \
        fadd_d \
        fadd_s \
        fclass_d \
@@ -190,7 +201,6 @@ riscv_insn_list = \
        fsub_d \
        fsub_s \
        fsw \
-       hrts \
        jal \
        jalr \
        lb \
@@ -203,8 +213,7 @@ riscv_insn_list = \
        lui \
        lw \
        lwu \
-       mrth \
-       mrts \
+       mret \
        mul \
        mulh \
        mulhsu \
@@ -217,12 +226,10 @@ riscv_insn_list = \
        remuw \
        remw \
        sb \
-       sbreak \
-       scall \
        sc_d \
        sc_w \
        sd \
-       sfence_vm \
+       sfence_vma \
        sh \
        sll \
        slli \