Abstract register read mostly working.

[riscv-isa-sim.git] / riscv / sim.cc

diff --git a/riscv/sim.cc b/riscv/sim.cc
index 461ae6ac211fb2d4e9420b91da4899e53613b5cf..033f12bc40983c211e09693037d56fcc8dcc2e26 100644 (file)
--- a/riscv/sim.cc
+++ b/riscv/sim.cc
@@ -41,7 +41,7 @@ sim_t::sim_t(const char* isa, size_t nprocs, size_t mem_mb, bool halted,
     fprintf(stderr, "warning: only got %zu bytes of target mem (wanted %zu)\n",
             memsz, memsz0);
 
-  bus.add_device(DEBUG_START, &debug_module);
+  debug_module.add_device(&bus);
 
   debug_mmu = new mmu_t(this, NULL);