Added PC histogram option.

[riscv-isa-sim.git] / riscv / sim.cc

diff --git a/riscv/sim.cc b/riscv/sim.cc
index 9020da4554082c147fecc9f9daf3bdf12ff9ffb9..9490af32c6d51b022b8936e9e7adce9ea0daa050 100644 (file)
--- a/riscv/sim.cc
+++ b/riscv/sim.cc
@@ -1,97 +1,142 @@
+// See LICENSE for license details.
+
 #include "sim.h"
 #include "htif.h"
-#include <sys/mman.h>
 #include <map>
 #include <iostream>
 #include <climits>
-#include <assert.h>
+#include <cstdlib>
+#include <cassert>
+#include <signal.h>
 
-#ifdef __linux__
-# define mmap mmap64
-#endif
+volatile bool ctrlc_pressed = false;
+static void handle_signal(int sig)
+{
+  if (ctrlc_pressed)
+    exit(-1);
+  ctrlc_pressed = true;
+  signal(sig, &handle_signal);
+}
 
-sim_t::sim_t(int _nprocs, htif_t* _htif)
-  : htif(_htif),
-    procs(_nprocs),
-    running(false)
+sim_t::sim_t(size_t nprocs, size_t mem_mb, const std::vector<std::string>& args)
+  : htif(new htif_isasim_t(this, args)), procs(std::max(nprocs, size_t(1))),
+    current_step(0), current_proc(0), debug(false)
 {
+  signal(SIGINT, &handle_signal);
   // allocate target machine's memory, shrinking it as necessary
   // until the allocation succeeds
-
-  size_t memsz0 = sizeof(size_t) == 8 ? 0x100000000ULL : 0x70000000UL;
-  size_t quantum = std::max(PGSIZE, (reg_t)sysconf(_SC_PAGESIZE));
-  memsz0 = memsz0/quantum*quantum;
+  size_t memsz0 = (size_t)mem_mb << 20;
+  size_t quantum = 1L << 20;
+  if (memsz0 == 0)
+    memsz0 = 1L << (sizeof(size_t) == 8 ? 32 : 30);
 
   memsz = memsz0;
-  mem = (char*)mmap(NULL, memsz, PROT_WRITE, MAP_PRIVATE|MAP_ANON, -1, 0);
+  while ((mem = (char*)calloc(1, memsz)) == NULL)
+    memsz = memsz*10/11/quantum*quantum;
 
-  if(mem == MAP_FAILED)
-  {
-    while(mem == MAP_FAILED && (memsz = memsz*10/11/quantum*quantum))
-      mem = (char*)mmap(NULL, memsz, PROT_WRITE, MAP_PRIVATE|MAP_ANON, -1, 0);
-    assert(mem != MAP_FAILED);
+  if (memsz != memsz0)
     fprintf(stderr, "warning: only got %lu bytes of target mem (wanted %lu)\n",
             (unsigned long)memsz, (unsigned long)memsz0);
-  }
 
-  mmu = new mmu_t(mem, memsz);
+  debug_mmu = new mmu_t(mem, memsz);
 
-  for(size_t i = 0; i < num_cores(); i++)
+  for (size_t i = 0; i < procs.size(); i++) {
     procs[i] = new processor_t(this, new mmu_t(mem, memsz), i);
+  }
 
-  htif->init(this);
 }
 
 sim_t::~sim_t()
 {
-  for(size_t i = 0; i < num_cores(); i++)
+  for (size_t i = 0; i < procs.size(); i++)
   {
-    mmu_t* pmmu = &procs[i]->mmu;
+    mmu_t* pmmu = procs[i]->get_mmu();
     delete procs[i];
     delete pmmu;
   }
-  delete mmu;
-  munmap(mem, memsz);
+  delete debug_mmu;
+  free(mem);
 }
 
-void sim_t::set_tohost(reg_t val)
+void sim_t::send_ipi(reg_t who)
 {
-  fromhost = 0;
-  tohost = val;
-  htif->wait_for_tohost_write();
+  if (who < procs.size())
+    procs[who]->deliver_ipi();
 }
 
-reg_t sim_t::get_fromhost()
+reg_t sim_t::get_scr(int which)
 {
-  htif->wait_for_fromhost_write();
-  return fromhost;
+  switch (which)
+  {
+    case 0: return procs.size();
+    case 1: return memsz >> 20;
+    default: return -1;
+  }
 }
 
-void sim_t::send_ipi(reg_t who)
+int sim_t::run()
 {
-  if(who < num_cores())
-    procs[who]->deliver_ipi();
+  while (htif->tick())
+  {
+    if (debug || ctrlc_pressed)
+      interactive();
+    else
+      step(INTERLEAVE);
+  }
+  return htif->exit_code();
 }
 
-void sim_t::run(bool debug)
+void sim_t::step(size_t n)
 {
-  htif->wait_for_start();
+  for (size_t i = 0, steps = 0; i < n; i += steps)
+  {
+    steps = std::min(n - i, INTERLEAVE - current_step);
+    procs[current_proc]->step(steps);
+
+    current_step += steps;
+    if (current_step == INTERLEAVE)
+    {
+      current_step = 0;
+      procs[current_proc]->yield_load_reservation();
+      if (++current_proc == procs.size())
+        current_proc = 0;
+
+      htif->tick();
+    }
+  }
+}
 
-  // start core 0
-  send_ipi(0);
+bool sim_t::running()
+{
+  for (size_t i = 0; i < procs.size(); i++)
+    if (procs[i]->running())
+      return true;
+  return false;
+}
 
-  for(running = true; running; )
-  {
-    if(!debug)
-      step_all(100,100,false);
-    else
-      interactive();
+void sim_t::stop()
+{
+  procs[0]->state.tohost = 1;
+  while (htif->tick())
+    ;
+}
+
+void sim_t::set_debug(bool value)
+{
+  debug = value;
+}
+
+void sim_t::set_histogram(bool value)
+{
+  histogram_enabled = value;
+  for (size_t i = 0; i < procs.size(); i++) {
+    procs[i]->set_histogram(histogram_enabled);
   }
 }
 
-void sim_t::step_all(size_t n, size_t interleave, bool noisy)
+void sim_t::set_procs_debug(bool value)
 {
-  for(size_t j = 0; j < n; j+=interleave)
-    for(int i = 0; i < (int)num_cores(); i++)
-      procs[i]->step(interleave,noisy);
+  for (size_t i=0; i< procs.size(); i++)
+    procs[i]->set_debug(value);
 }
+