Added PC histogram option.

[riscv-isa-sim.git] / riscv / sim.cc

diff --git a/riscv/sim.cc b/riscv/sim.cc
index f01e931ea6eb24f153feabdb1f84e5283dfe5d97..9490af32c6d51b022b8936e9e7adce9ea0daa050 100644 (file)
--- a/riscv/sim.cc
+++ b/riscv/sim.cc
@@ -34,14 +34,16 @@ sim_t::sim_t(size_t nprocs, size_t mem_mb, const std::vector<std::string>& args)
   while ((mem = (char*)calloc(1, memsz)) == NULL)
     memsz = memsz*10/11/quantum*quantum;
 
-  if (memsz != memsz)
+  if (memsz != memsz0)
     fprintf(stderr, "warning: only got %lu bytes of target mem (wanted %lu)\n",
             (unsigned long)memsz, (unsigned long)memsz0);
 
   debug_mmu = new mmu_t(mem, memsz);
 
-  for (size_t i = 0; i < procs.size(); i++)
+  for (size_t i = 0; i < procs.size(); i++) {
     procs[i] = new processor_t(this, new mmu_t(mem, memsz), i);
+  }
+
 }
 
 sim_t::~sim_t()
@@ -72,23 +74,24 @@ reg_t sim_t::get_scr(int which)
   }
 }
 
-void sim_t::run()
+int sim_t::run()
 {
-  while (!htif->done())
+  while (htif->tick())
   {
     if (debug || ctrlc_pressed)
       interactive();
     else
-      step(INTERLEAVE, false);
+      step(INTERLEAVE);
   }
+  return htif->exit_code();
 }
 
-void sim_t::step(size_t n, bool noisy)
+void sim_t::step(size_t n)
 {
   for (size_t i = 0, steps = 0; i < n; i += steps)
   {
     steps = std::min(n - i, INTERLEAVE - current_step);
-    procs[current_proc]->step(steps, noisy);
+    procs[current_proc]->step(steps);
 
     current_step += steps;
     if (current_step == INTERLEAVE)
@@ -99,8 +102,6 @@ void sim_t::step(size_t n, bool noisy)
         current_proc = 0;
 
       htif->tick();
-      if (!running())
-        break;
     }
   }
 }
@@ -116,6 +117,26 @@ bool sim_t::running()
 void sim_t::stop()
 {
   procs[0]->state.tohost = 1;
-  while (!htif->done())
-    htif->tick();
+  while (htif->tick())
+    ;
+}
+
+void sim_t::set_debug(bool value)
+{
+  debug = value;
+}
+
+void sim_t::set_histogram(bool value)
+{
+  histogram_enabled = value;
+  for (size_t i = 0; i < procs.size(); i++) {
+    procs[i]->set_histogram(histogram_enabled);
+  }
 }
+
+void sim_t::set_procs_debug(bool value)
+{
+  for (size_t i=0; i< procs.size(); i++)
+    procs[i]->set_debug(value);
+}
+